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Signal scheduling driven circuit partitioning for multiple fpgas with time-multiplexed interconnection.
| Content Provider | CiteSeerX |
|---|---|
| Author | Kwon, Young-Su Yang, Woo-Seung Kyung, Chong-Min |
| Abstract | FPGA-based logic emulator with large gate capacity generally comprises a large number of FPGAs. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several stateof-the-art FPGAs. This paper proposes a circuit partitioning algorithm called SCATOMi(SCheduling driven Algorithm for TOMi) for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(Time-multiplexed, Off-chip, Multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Experiments on architecture comparison show that, by adopting the proposed TOMi interconnection architecture along with SCATOMi, the pin count is reduced to 15.2%-81.3 % while the critical path delay is reduced to 46.1%-67.6 % compared to traditional architectures including mesh, crossbar and VirtualWire architecture. 1 |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Multiple Fpgas Fpga-based Logic Emulator Time-multiplexed Interconnection Tomi Interconnection Architecture Several Stateof-the-art Fpgas Inter-fpga Signal Transfer Interconnection Architecture Critical Path Traditional Architecture Multicasting Interconnection Interconnection Wire Gate Utilization Tomi Architecture Traditional Partitioning Algorithm Virtualwire Architecture Signal Scheduling Driven Circuit Partitioning Architecture Comparison Show Pin Count Signal Pin Large Number Large Gate Capacity Logic Emulator Critical Path Delay Multi-fpga System |
| Content Type | Text |
| Resource Type | Article |
