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Design for manufacturibity the impact on the physical design stage and flow (2004).
| Content Provider | CiteSeerX |
|---|---|
| Author | Rittman, Danny |
| Abstract | In this paper I present the impact of sub-wavelength optical lithography for new EDA tools, IC Layout Design flows and manufacturability. We discuss the necessity of corrections for optical process effects (optical proximity correction (OPC) and phase-shifting masks (PSM)) and will focus on the implications of OPC and PSM for layout design and verification methodologies. Our discussion addresses the necessary changes in the design-to-manufacturing flow, including infrastructure development in the mask and process communities as well as opportunities for research and development in IC physical layout and verification stage. Reticle enhancement technologies (RET) like optical proximity correction (OPC) and phase shift masking (PSM) have significantly increased the cost and complexity of sub-micron nanometer photomasks. The photomask layout is no longer an exact replica of the design layout. As a result, reliably verifying RET synthesis accuracy, structural integrity, and conformance to mask fabrication rules are crucial for the manufacture of nanometer regime VLSI designs. New EDA systems were recently developed consists of efficient wafer-patterning simulators that is able to solve the process physical equations for optical imaging, resist development and hence can achieve high degree accuracy required by mask verification tasks. These tools are able to efficiently evaluate mask performance by simulating edge displacement errors between wafer image and the intended layout. I’ll discuss the capabilities for hot spot detection, line width variation analysis, and process window prediction capabilities with a sample practical layout. I’ll also elaborate the potential of the new physical model simulator for improving circuit performance in physical layout synthesis. |
| File Format | |
| Publisher Date | 2004-01-01 |
| Access Restriction | Open |
| Subject Keyword | Physical Design Stage Optical Proximity Correction Process Window Prediction Capability Mask Verification Task Physical Layout Synthesis Exact Replica Photomask Layout Edge Displacement Error Design Layout Nanometer Regime Vlsi Design Hot Spot Detection Sub-wavelength Optical Lithography Optical Imaging Wafer Image Verification Methodology Process Community Sub-micron Nanometer Photomasks Process Physical Equation Layout Design Infrastructure Development Design-to-manufacturing Flow Structural Integrity Line Width Variation Analysis Necessary Change Fabrication Rule Circuit Performance New Physical Model Simulator Ic Physical Layout Phase-shifting Mask Resist Development Sample Practical Layout Efficient Wafer-patterning Simulator New Eda Tool Reticle Enhancement Technology Ret Synthesis Accuracy Mask Performance New Eda System Optical Process Effect Phase Shift Masking High Degree Accuracy Verification Stage Ic Layout Design |
| Content Type | Text |
| Resource Type | Article |
