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Adoption of OPC and the Impact on Design and Layout (2001)
| Content Provider | CiteSeerX |
|---|---|
| Author | Schellenberg, F. M. Toublan, Schellenberg Olivier Toublan, Olivier |
| Description | Proc. Design Automation Conf |
| Abstract | With the adoption of various combinations of resolution enhancement techniques (RET) for IC lithography, different process constraints are placed on the IC layout. The final layout used for mask production is dramatically different than the original designer's intent. To insure that EDA tools developed for applying RET techniques can have optimal performance, layout methodology must change to create a true "target" layer that represents the actual design intent. Verification of the final layout is then expanded from LVS and DRC to also include lithography process simulation, which compares results to this desired "target" and governs the application of RET. |
| File Format | |
| Publisher Date | 2001-01-01 |
| Access Restriction | Open |
| Subject Keyword | Actual Design Intent Lithography Process Simulation Optimal Performance Original Designer Mask Production Eda Tool Ic Lithography Resolution Enhancement Technique Ic Layout Different Process Constraint Final Layout Ret Technique Various Combination True Target Layer |
| Content Type | Text |
