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The Performance of the Cedar Multistage Switching Network (1997)
| Content Provider | CiteSeerX |
|---|---|
| Author | Zhang, Zheng Torrellas, Josep |
| Abstract | While multistage switching networks for vector multiprocessors have been studied extensively, detailed evaluations of their performance are rare. Indeed, analytical models, simulations with pseudo-synthetic loads, studies focused on average-value parameters, and measurements of networks disconnected from the machine, all provide limited information. In this paper, instead, we present an in-depth empirical analysis of a multistage switching network in a realistic setting: we use hardware probes to examine the performance of the omega network of the Cedar sharedmemory machine executing real applications. The machine is configured with 16 vector processors. The analysis suggests that the performance of multistage switching networks is limited by traffic non-uniformities. We identify two major non-uniformities that degrade Cedar's performance and are likely to slow down other networks too. The first one is the contention caused by the return messages in a vector access as they converge fro... |
| File Format | |
| Journal | IEEE Transactions on parallel and distributed systems |
| Journal | IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS |
| Journal | IEEE Transactions on Parallel and Distributed Systems |
| Publisher Date | 1997-01-01 |
| Access Restriction | Open |
| Subject Keyword | In-depth Empirical Analysis Hardware Probe Limited Information Vector Processor Average-value Parameter Omega Network Pseudo-synthetic Load Detailed Evaluation Analytical Model Cedar Multistage Switching Network First One Return Message Real Application Major Non-uniformities Cedar Sharedmemory Machine Traffic Non-uniformities Vector Access Vector Multiprocessor Realistic Setting |
| Content Type | Text |
