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| Content Provider | ACM Digital Library |
|---|---|
| Author | Torrellas, Josep Zhang, Zheng |
| Abstract | While multistage switching networks for vector multiprocessors have been studied extensively, detailed evaluations of their performance are rare. Indeed, analytical models, simulations with pseudo-synthetic loads, studies focused on average-value parameters, and measurements of networks disconnected from the machine, all provide limited information. In this paper, instead, we present an in-depth empirical analysis of a multistage switching network in a realistic setting: we use hardware probes to examine the performance of the omega network of the Cedar shared-memory machine executing real applications. The machine is configured with 16 vector processors.The analysis suggests that the performance of multistage switching networks is limited by traffic non-uniformities. We identify two major non-uniformities that degrade Cedar's performance and are likely to slow down other networks too. The first one is the contention caused by the return messages in a vector access as they converge from the memories to one processor port. This traffic convergence penalizes vector reads and, more importantly, causes tree saturation. The second non-uniformity is the uneven contention delays induced by even a relatively fair scheme to resolve message collisions. Based on our observations, we argue that intuitive optimizations for multistage switching networks may not be cost-effective. Instead, we suggest changes to increase the network bandwidth at the root of the traffic convergence tree and to delay traffic convergence up until the final stages of the network. |
| Starting Page | 265 |
| Ending Page | 274 |
| Page Count | 10 |
| File Format | |
| ISBN | 0818666056 |
| ISSN | 10639535 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 1994-11-14 |
| Access Restriction | Subscribed |
| Content Type | Text |
| Resource Type | Article |
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