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Board-level component modeling using vital.
| Content Provider | CiteSeerX |
|---|---|
| Author | Vreeland, Russell E. |
| Abstract | The VITAL 95 standard for VHDL libraries was written primarily to solve the problem of developing consistent ASIC libraries with VHDL. This paper discusses how a design methodology for board design with board-level simulation models written in VITAL can be advantageous, and outlines lessons-learned at TRW over the past couple of years in implementing board-level component libraries in VITAL/VHDL. The most notable advantage of developing board-level simulation models in VHDL is the seamless simulation environment when integrating board-level simulations with both behavioral simulations (systems level simulations) and FPGA and ASIC simulations-assuming they are VHDL-based. There is a |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Board-level Component Board-level Simulation Model Vital Vhdl Board-level Simulation Behavioral Simulation Notable Advantage Vhdl Library Board Design Seamless Simulation Environment Past Couple Design Methodology Consistent Asic Library Board-level Component Library Asic Simulations-assuming |
| Content Type | Text |
| Resource Type | Article |
