Loading...
Please wait, while we are loading the content...
Similar Documents
A vhdl-ams simulation methodology for transient supply current extraction (2002).
| Content Provider | CiteSeerX |
|---|---|
| Author | Trullemans, Anne-Marie Perdriau, Richard Ramdani, Mohamed Lambert, Damien Levant, Jean-Luc |
| Abstract | Transient supply current extraction plays a very important role in estimating performance level in the IC EMC field. As far as complex circuits such as microcontrollers are concerned, transistor-level (SPICE-based) simulation leads to very long CPU times, mainly because of memory arrays which often represent more than 80 % of the transistors in a microcontroller. A convenient way of cutting out simulation times is to describe memories at the behavioral level, while keeping the microcontroller core itself at the structural level. In the first step, the dynamic supply current consumption of the microcontroller core alone is simulated by coupling purely digital (VITAL) VHDL models for Flash and RAM blocks to the transistor-level core. The next step consists in adding VHDL-AMS behavioral models of the consumption of the memory blocks themselves to the VITAL descriptions. This allows the designer to simulate the whole microcontroller without dramatically increasing simulation time. This work is supported by the MESDIE project and complies with the ICEM proposal. |
| File Format | |
| Publisher Date | 2002-01-01 |
| Access Restriction | Open |
| Subject Keyword | Vhdl-ams Behavioral Model Vhdl-ams Simulation Methodology Important Role First Step Complex Circuit Transient Supply Current Extraction Transistor-level Core Vhdl Model Convenient Way Icem Proposal Dynamic Supply Current Consumption Vital Description Next Step Microcontroller Core Mesdie Project Structural Level Ic Emc Field Memory Array Microcontroller Core Alone Simulation Time Performance Level Behavioral Level Whole Microcontroller Ram Block Cpu Time |
| Content Type | Text |
