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Analysis filter bank module.
| Content Provider | CiteSeerX |
|---|---|
| Author | Agarwal, Nainesh Dimopoulos, Nikitas |
| Abstract | For rapidly prototyping hardware architectures, we have developed a system level design language, called CoDeL (Controller Description Language) [1]–[4]. CoDeL targets the specification and design at the behavioral level. Details of the platform and the language syntax can be found in [1], [2]. We have now developed extensions to the CoDeL compiler which implement clock gating to dramatically lower dynamic power dissipation in CMOS VLSI circuits. This mechanism disables the clock to the registers during periods when we are ensured that the registers are inactive. To estimate these power savings from automated clock gating, we have developed an analysis framework, which allows quick and accurate power savings estimation based on the description at the behavioral level. This estimation framework is built into the CoDeL compiler and the estimates are output upon compilation of an design. To evaluate CoDeL’s power efficient compilation we use an implementation of a 5/3 Discrete Wavelet Transform using the lifting technique. A detailed description can be found in [4]. We have implemented the forward and inverse DWT using three separate modules (see figure 1): the 5/3 analysis filter bank module, the 5/3 synthesis filter bank module, and the DWT module. All the modules are implemented using CoDeL. For synthesis we have used Synopsys tools with the TSMC 0.18-micron CMOS technology. Table I shows a comparison of the power savings that are predicted by the estimation framework and what we obtain from power analysis using Synopsys. The power results from Synopsys come from two methods. One uses statistical switching activity for the various elements of the circuit, while the other uses switching activity annotated through simulation. The statistical power analysis provides a better comparison for our estimation framework, since they are both based on a static |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Analysis Filter Bank Module Estimation Framework Behavioral Level Codel Compiler Power Saving Synopsys Tool Power Analysis Accurate Power Saving Estimation Dynamic Power Dissipation Synthesis Filter Bank Module Hardware Architecture Dwt Module Power Result Detailed Description Controller Description Language Discrete Wavelet Transform Implement Clock Statistical Switching Activity Analysis Framework Cmos Vlsi Circuit Inverse Dwt Clock Gating Lifting Technique System Level Design Language Statistical Power Analysis Codel Power Efficient Compilation Various Element Separate Module 18-micron Cmos Technology Language Syntax |
| Content Type | Text |
