A dspstone benchmark of codel’s automated clock gating platform.

Article

Analysis filter bank module.

Power efficient rapid hardware development using CoDel and automated clock gating

Article

High-level FSMD design and automated clock gating with CoDeL

Article

Power efficient rapid system prototyping using CoDel: the 2D DWT using lifting

Article

Efficient parallel hardware architecture for Lifting-Based discrete wavelet transform

Article

INTERCONNECT CENTRIC FRAMEWORK FOR LOW-POWER ARCHITECTURE SYNTHESIS IMPLEMENTING A CLASS OF DISCRETE ORTHOGONAL WAVELET TRANSFORM USING ARRAY PROCESSOR

Clock-Tree Power Optimization based on RTL Clock-Gating Monica Donno

Article

Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform (2004)

Article