NDLI: Methods for modeling resource contention on simultaneous multithreading processors.

Please wait, while we are loading the content...

Methods for modeling resource contention on simultaneous multithreading processors.

Content Provider	CiteSeerX
Abstract	Simultaneous multithreading (SMT) seeks to improve the computation throughput of a processor core by sharing pri-mary resources such as functional units, issue bandwidth, and caches. SMT designs increase utilization and generally improve overall throughput, but the amount of improvement is highly dependent on competition for shared resources be-tween the scheduled threads. This variability has implica-tions that relate to operating system scheduling, simulation techniques, and fairness. Although these techniques recog-nize the implications of thread interaction, they do little to profile and predict this interaction. The modeling approach presented in this paper uses data collected from performance counters on two different hard-ware implementations of Pentium-4 Hyper-Threading pro-cessors to demonstrate the effects of thread interaction. Techniques are described for fitting linear regression mod-els and recursive partitioning to use the counters to make online predictions of performance (expressed as instruc-tions per cycle); these predictions can be used by the oper-ating system to guide scheduling decisions. A detailed anal-ysis of the effectiveness of each of these techniques is pre-sented. 1.
File Format	PDF
Access Restriction	Open
Subject Keyword	Modeling Resource Contention Simultaneous Multithreading Processor Thread Interaction Issue Bandwidth Detailed Anal-ysis System Scheduling Processor Core Simultaneous Multithreading Pentium-4 Hyper-threading Pro-cessors Scheduled Thread Different Hard-ware Implementation Shared Resource Computation Throughput Recursive Partitioning Pri-mary Resource Oper-ating System Simulation Technique Performance Counter Functional Unit Online Prediction Linear Regression Mod-els Overall Throughput
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in