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Physical experimentation with prefetching helper threads on intel’s hyper-threaded processors (2004)
| Content Provider | CiteSeerX |
|---|---|
| Author | Kim, Dongkeun Liao, Steve Shih-Wei Wang, Perry H. Cuvillo, Juan Del Tian, Xinmin Wang, Hong Yeung, Donald Girkar, Milind Shen, John P. |
| Description | Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution techniques based on hardware, compiler, or both have been proposed and studied extensively by researchers. They report promising results on simulators that model a Simultaneous Multithreading (SMT) processor. In this paper, we apply the helper threading idea on a real multithreaded machine, i.e., Intel Pentium 4 processor with Hyper-Threading Technology, and show that indeed it can provide wall-clock speedup on real silicon. To achieve further performance improvements via helper threads, we investigate three helper threading scenarios that are driven by automated compiler infrastructure, and identify several key challenges and opportunities for novel hardware and software optimizations. Our study shows a program behavior changes dynamically during execution. In addition, the organizations of certain critical hardware structures in the hyper-threaded processors are either shared or partitioned in the multi-threading mode and thus, the tradeoffs regarding resource contention can be intricate. Therefore, it is essential to judiciously invoke helper threads by adapting to the dynamic program behavior so that we can alleviate potential performance degradation due to resource contention. Moreover, since adapting to the dynamic behavior requires frequent thread synchronization, having light-weight thread synchronization mechanisms is important. 1. |
| File Format | |
| Language | English |
| Publisher | IEEE Computer Society |
| Publisher Date | 2004-01-01 |
| Publisher Institution | InCGO ’04: Proceedings of the international |
| Access Restriction | Open |
| Subject Keyword | Performance Improvement Real Multithreaded Machine Memory Latency Cache Block Light-weight Thread Synchronization Mechanism Program Behavior Change Software Optimization Several Key Challenge Novel Hardware Helper Thread Frequent Thread Synchronization Hyper-threading Technology Real Silicon Intel Hyper-threaded Processor Dynamic Behavior Resource Contention Dynamic Program Behavior Effective Way Potential Performance Degradation Physical Experimentation Much Attention Pre-execution Technique Wall-clock Speedup Multi-threading Mode Simultaneous Multithreading Automated Compiler Infrastructure Certain Critical Hardware Structure Hyper-threaded Processor Intel Pentium |
| Content Type | Text |
| Resource Type | Article |
