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Dynamic MIPS rate stabilization in out-of-order processors (2009)
| Content Provider | CiteSeerX |
|---|---|
| Author | Suh, Jinho Dubois, Michel |
| Description | Today’s micro-processor cores reach high performance levels not only by their high clock rate but also by the concurrent execution of a large number of instructions. Because of the relationship between power and frequency, it becomes attractive to run an OoO (Out-of-Order) processor at a frequency lower than its nominal frequency in the context of embedded or real-time systems. Unfortunately, whereas OoO processors have high average throughput, their highly variable and hard-to-predict execution rate make them unsuitable for real-time systems with hard or even soft deadlines. In this paper, we show that the throughput of an OoO processor can be stable and predictable by controlling its MIPS (Mega Instructions Per Second) rate via a PID (Proportional, Integral, and Differential gain) feedback controller and DVFS (Dynamic Voltage and Frequency Scaling). The controller controls on-chip supply voltage (Vdd) and operating frequency in order to sustain a target MIPS rate. The stabilized processor uses much less power per committed instruction, because of its reduced average frequency. The EPI (Energy Per Instruction) is also lowered by an average of 28% across our benchmark programs. Since a stable MIPS rate is maintained consistently and power/ energy per instruction is reduced, OoO processors stabilized by a feedback controller can realistically be deployed in real-time systems with soft or hard deadlines. To demonstrate this capability we select a subset of the MiBench benchmarks that display the widest execution rate variations and stabilize their MIPS rate in the context of a 1GHz Pentium III-like micro-architecture. 1. |
| File Format | |
| Language | English |
| Publisher Date | 2009-01-01 |
| Publisher Institution | in ISCA-36 |
| Access Restriction | Open |
| Subject Keyword | Out-of-order Processor Dynamic Voltage Execution Rate Variation On-chip Supply Voltage Benchmark Program High Average Throughput Reduced Average Frequency Mega Instruction Per Second Mips Rate Concurrent Execution Power Energy Differential Gain Soft Deadline Frequency Scaling Target Mips Rate Hard-to-predict Execution Rate Real-time System Energy Per Instruction Nominal Frequency Feedback Controller Stable Mips Rate Micro-processor Core Large Number Hard Deadline Stabilized Processor Mibench Benchmark High Clock Rate Dynamic Mips Rate Stabilization High Performance Level Pentium Iii-like Micro-architecture Ooo Processor |
| Content Type | Text |
| Resource Type | Article |
