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Reducing data hazards on multi-pipelined dsp architecture with loop scheduling (1998).
| Content Provider | CiteSeerX |
|---|---|
| Author | Tongsima, Sissades Chantrapornchai, Chantana Sha, Edwin H. -M. Passos, Nelson L. |
| Abstract | Computation intensive DSP applications usually require parallel/pipelined processors in order to meet specific timing requirements. Data hazards are a major obstacle against the high performance of pipelined systems. This paper presents a novel efficient loop scheduling algorithm that reduces data hazards for such DSP applications. This algorithm has been embedded in a tool, called SHARP, which schedules a pipelined data flow graph to multiple pipelined units while hiding the underlying data hazards and minimizing the execution time. This paper reports significant improvement for some well-known benchmarks showing the efficiency of the scheduling algorithm and the flexibility of the simulation tool. ###################################################################################################### ################################ ##########(parallel/pipelined processors) ############################## ######## ##################### ### #####################################... |
| File Format | |
| Publisher Date | 1998-01-01 |
| Access Restriction | Open |
| Subject Keyword | Data Hazard Multi-pipelined Dsp Architecture Pipelined System Significant Improvement Pipelined Data Flow Graph Scheduling Algorithm Pipelined Unit Execution Time Dsp Application Major Obstacle High Performance Specific Timing Requirement Well-known Benchmark Computation Intensive Dsp Application Novel Efficient Loop Parallel Pipelined Processor Simulation Tool |
| Content Type | Text |
| Resource Type | Article |
