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An Accurate and Efficient Simulation-Based Analysis for Worst Case (2006)
| Content Provider | CiteSeerX |
|---|---|
| Author | Nakashima, Hiroshi Konishi, Masahiro Nakada, Takashi |
| Description | This paper proposes an efficient method to analyze worst case interruption delay (WCID) of a workload running on modern microprocessors using a cycle accurate simulator (CAS). Our method is highly accurate because it simulates all possible cases inserting an interruption just before the retirement of every instruction executed in a workload. It is also (reasonably) efficient because it takes O(N log N) time for a workload with N executed instructions, instead of O(N 2) of a straightforward iterative simulation of interrupted executions. The key idea for the efficiency is that a pair of executions with different interruption points has a set of durations in which they behave exactly coherent and thus one of simulations for the durations may be omitted. We implemented this method modifying the SimpleScalar tool set to prove it finds out WCID of workloads with five million executed instructions in reasonable time, less than 30 minutes, which would be 200–300 days by the straightforward method. We also show a parallelization of our method achieves a good speedup, about 7-fold with 8-node PC cluster. |
| File Format | |
| Language | English |
| Publisher Date | 2006-01-01 |
| Publisher Institution | Interruption Delay, CASES 2006 |
| Access Restriction | Open |
| Subject Keyword | Interrupted Execution Simplescalar Tool Straightforward Method Cycle Accurate Simulator Efficient Simulation-based Analysis Case Interruption Delay Possible Case 8-node Pc Cluster Modern Microprocessor Good Speedup Key Idea Efficient Method Reasonable Time Different Interruption Point Worst Case Straightforward Iterative Simulation |
| Content Type | Text |
| Resource Type | Article |
