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Workshop on the intersections of computer architecture and reconfigurable logic (carl 2012): category 1 venice: a compact vector processor for fpga applications.
| Content Provider | CiteSeerX |
|---|---|
| Author | Severance, Aaron Lemieux, Guy |
| Abstract | Abstract—This paper presents VENICE, a new soft vector processor (SVP) for FPGA applications. VENICE differs from previous SVPs in that it was designed for maximum throughput with a small number (1 to 4) of ALUs. By increasing clockspeed and eliminating bottlenecks in ALU utilization, VENICE can achieve over 2x better performance-per-logic block than VEGAS, the previous best SVP. VENICE is also simpler to program, uses standard C pointers into a scratchpad memory rather than vector registers, and has no penalty for unaligned data. Keywords-vector; SIMD; soft processors; scratchpad memory; FPGA; I. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Fpga Application Computer Architecture Reconfigurable Logic Compact Vector Processor Scratchpad Memory Maximum Throughput Unaligned Data Performance-per-logic Block Previous Svps Venice Differs New Soft Vector Processor Standard Pointer Vector Register Soft Processor Alu Utilization Small Number |
| Content Type | Text |
