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Turboscalar: A High Frequency High IPC Microarchitecture (2000)
| Content Provider | CiteSeerX |
|---|---|
| Author | Black, Bryan Shen, John Paul |
| Description | There is significant performance motivation to build larger and wider superscalar machines, however the implementation complexity can be overwhelming. When superscalar machines grow they necessarily become deeper in order to maintain frequency. As the pipeline depth increases the performance gained by a wide instruction fetch and dispatch is lost to branch misprediction penalty cycles. This work proposes the new Turboscalar microarchitecture, which is strongly based on the superscalar paradigm. Turboscalar utilizes run time information to optimize instruction execution. This new microarchitecture increases performance by reducing implementation complexity, allowing the construction of very shallow wide pipelines, which yield high performance. Results: A realistic Turboscalar implementation is proposed, that improves performance 66% over a wide deep superscalar that utilizes a block-based trace cache. 1 Introduction Most technologists anticipate the continuation of Moore's l... |
| File Format | |
| Language | English |
| Publisher Date | 2000-01-01 |
| Publisher Institution | In Workshop on Complexity-Effective Design, International Symposium on Computer Architecture |
| Access Restriction | Open |
| Subject Keyword | Shallow Wide Pipeline Superscalar Paradigm Implementation Complexity Significant Performance Motivation Pipeline Depth Wide Instruction Fetch High Frequency High Ipc Microarchitecture Wide Deep Superscalar High Performance Instruction Execution Block-based Trace Cache New Turboscalar Microarchitecture Realistic Turboscalar Implementation New Microarchitecture Increase Performance Misprediction Penalty Cycle Turboscalar Utilizes Run Time Information Superscalar Machine |
| Content Type | Text |
| Resource Type | Article |
