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Worst case delay analysis for memory interference in multicore systems
| Content Provider | CiteSeerX |
|---|---|
| Author | Pellizzoni, Rodolfo Thiele, Lothar Caccamo, Marco Chen, Jian-Jia Schranzhofer, Andreas |
| Description | In Proceedings of the Conference on Design, Automation and Test in Europe. DATE ’10. European Design and Automation Association, 3001 |
| Abstract | Abstract—Employing COTS components in real-time embedded systems leads to timing challenges. When multiple CPU cores and DMA peripherals run simultaneously, contention for access to main memory can greatly increase a task’s WCET. In this paper, we introduce an analysis methodology that computes upper bounds to task delay due to memory contention. First, an arrival curve is derived for each core representing the maximum memory traffic produced by all tasks executed on it. Arrival curves are then combined with a representation of the cache behavior for the task under analysis to generate a delay bound. Based on the computed delay, we show how tasks can be feasibly scheduled according to assigned time slots on each core. I. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Multicore System Task Wcet Assigned Time Slot Abstract Employing Cot Component Maximum Memory Traffic Dma Peripheral Delay Bound Cache Behavior Memory Interference Upper Bound Worst Case Delay Analysis Analysis Methodology Memory Contention Main Memory Real-time Embedded System Multiple Cpu Core Computed Delay Arrival Curve |
| Content Type | Text |
| Resource Type | Proceeding |
