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Multipldpass pipelining: enhancing in-order microarchitectures to out-of-order performance (2005).
| Content Provider | CiteSeerX |
|---|---|
| Author | Barnes, Ronald D. |
| Abstract | Out-of-program-order execution has become almost a ubiquitous characteristic of modern processors because of its ability to tolerate variable memory-instruction latency. As designs are becoming increasingly power-conscious, the cost and complexity of the components of out-of-order execution are becoming problematic. Compilers have generally proven adept at planning useful static instruction-level parallelism, but relying solely on the compiler's instruction arrangement has been shown to perform poorly when cache misses occur. This work proposes two multiple-pass pipelining "flea-flicker" microarchitectural techniques, two-pass pipelining and multipass pipelining, both of which exploit a static compiler's meticulous scheduling as well as advance execution beyond otherwise stalled instructions without the complexity of true out-of-order execution. With twopass pipelining, programs execute on two in-order back-end pipelines coupled by a queue. The "advance" pipeline often defers instructions dispatching with unready operands rather than stalling. The "backup" pipeline allows concurrent resolution of instructions deferred by the first pipeline allowing overlapping of useful "advanced" execution with miss resolution. Multipass pipelining is based upon a similar lll concept, but overcomes the shortfalls of two-pass pipelining through simultaneous execution of architectural and advance instructions on a common pipeline in a simultaneous multithreading-like fashion. These techniques perform similarly to achievable out-of-order designs while comparing favorably in terms of power and complexity. An accompanying compiler technique and instruction marking further enhances the handling of miss latencies and reduces fruitless speculative execution by statically denoting instructions that, when stalled, indicate there is little opportunity for advanced execution. |
| File Format | |
| Publisher Date | 2005-01-01 |
| Access Restriction | Open |
| Subject Keyword | Enhancing In-order Microarchitectures Out-of-order Performance Multipldpass Pipelining Multipass Pipelining Two-pass Pipelining Ubiquitous Characteristic Miss Resolution Miss Latency Advance Execution Out-of-program-order Execution Meticulous Scheduling Little Opportunity Speculative Execution Advance Pipeline Simultaneous Execution True Out-of-order Execution Modern Processor Instruction Arrangement Static Compiler Concurrent Resolution Simultaneous Multithreading-like Fashion Achievable Out-of-order Design Variable Memory-instruction Latency Similar Lll Concept Advance Instruction Out-of-order Execution In-order Back-end Pipeline Compiler Technique Useful Static Instruction-level Parallelism Common Pipeline First Pipeline Backup Pipeline Advanced Execution Flea-flicker Microarchitectural Technique Twopass Pipelining Unready Operand |
| Content Type | Text |
