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Performance driven resynthesis by exploiting retiming-induced state register equivalence (1999).
| Content Provider | CiteSeerX |
|---|---|
| Author | Kalla, Priyank Ciesielski, Maciej J. |
| Abstract | : This paper presents a retiming and resynthesis technique for cycle-time minimization of sequential circuits circuits with feedbacks (finite state machines). Operating on the delay critical paths of the circuit, we perform a set of controlled local retimings of registers across fanout stems and logic gates, followed by local node simplifications. We guide the retiming of registers across fanout stems to induce equivalence relations among them, which are exploited for subsequent logic simplification. Our technique is able to analyze correlation of logic across register boundaries during simplification. We strive to minimize the increase in number of registers without sacrificing the cycle-time performance. The results demonstrate a favourable performance /area trade-off when compared with optimally retimed circuits. I. INTRODUCTION Conventional sequential synthesis techniques apply a variety of heuristic transformations that target the optimization of the combinational logic component... |
| File Format | |
| Publisher Date | 1999-01-01 |
| Access Restriction | Open |
| Subject Keyword | Performance Driven Resynthesis Retiming-induced State Register Equivalence Favourable Performance Area Trade-off Cycle-time Performance Heuristic Transformation Subsequent Logic Simplification Equivalence Relation Local Node Simplification Combinational Logic Component Finite State Machine Delay Critical Path Controlled Local Retimings Sequential Circuit Circuit Resynthesis Technique Logic Gate Introduction Conventional Sequential Synthesis Technique Fanout Stem Cycle-time Minimization Register Boundary |
| Content Type | Text |
| Resource Type | Article |
