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6b-5 a high-throughput low-power aes cipher for network applications.
| Content Provider | CiteSeerX |
|---|---|
| Author | Lin, Shin-Yi Huang, Chih-Tsun |
| Abstract | Abstract—We propose a full-featured high-throughput lowpower AES cipher which is suitable for widespread network applications. Different modes of operation are implemented, i.e., the ECB, CBC, CTR and CCM modes. Our cipher utilizes a costefficient two-stage pipeline for the CCM mode by a single datapath. With the design-for-test circuitry, the maximum throughput is 4.27 Gbps using a 0.13�m CMOS technology with a 333MHz clock rate. The hardware cost is 86.2K gates with the power of |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Network Application High-throughput Low-power Aes Cipher Ccm Mode Maximum Throughput Costefficient Two-stage Pipeline Different Mode Hardware Cost Widespread Network Application Single Datapath Cmos Technology Full-featured High-throughput Lowpower Aes Cipher Design-for-test Circuitry Clock Rate |
| Content Type | Text |
