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Architectural Design Features of a Programmable High Throughput AES Coprocessor (2004)
| Content Provider | CiteSeerX |
|---|---|
| Author | Hodjat, Alireza Schaumont, Patrick Verbauwhede, Ingrid |
| Description | Programmable, high throughput domain specific crypto processors are required for different networking applications. This paper presents the architectural design features that lead to a multiple Gbits/s rate AES coprocessor, which is programmable with domain specific instructions for Gbit throughput IPSec and other applications. Our design is a loosely coupled, independently working crypto-coprocessor that runs AES in ECB, CBC-MAC, Counter, and CCM modes of operation at a maximum throughput of 3.43 Gbits/s in a 0.18-#m CMOS technology without any penalty in throughput for any of the above modes. |
| File Format | |
| Language | English |
| Publisher Date | 2004-01-01 |
| Publisher Institution | AES Coprocessor, in the proceedings of ITCC 2004, vol 2, pp 498-502, Las Vegas |
| Access Restriction | Open |
| Subject Keyword | Maximum Throughput Architectural Design Feature Programmable High Throughput Aes Coprocessor Multiple Gbit Rate Aes Coprocessor Cmos Technology Domain Specific Instruction Ccm Mode Gbit Throughput Ipsec Different Networking Application |
| Content Type | Text |
| Resource Type | Article |
