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An Efficient Bandwidth Utilized FFT Computation using Highly Accelerated Advanced Multiplier
| Content Provider | Semantic Scholar |
|---|---|
| Author | Poorna, M. Jyothi Sri, M. D. Kamala |
| Copyright Year | 2017 |
| Abstract | During last decades demand for integrated circuits design increases in order to meet the requirement of High speed, High throughput and area efficient. In Digital Signal Processing systems Fast Multipliers are essential. The speed of the multiplication is important not only in digital signal processing but also in general purpose processors. Here a Fast Fourier transform is implement using twin precision technique. By adapting efficient multipliers to the bit widths of the operands reduce the dissipation of power. Computational throughput is increased by performing narrow-width operation in parallel. Efficient bandwidth utilization can be achieved by using twin-precision technique with Baugh-Wooley algorithm. |
| Starting Page | 27 |
| Ending Page | 30 |
| Page Count | 4 |
| File Format | PDF HTM / HTML |
| DOI | 10.14445/23488549/ijece-v4i3p108 |
| Volume Number | 4 |
| Alternate Webpage(s) | http://www.internationaljournalssrg.org/IJECE/2017/Volume4-Issue3/IJECE-V4I3P108.pdf |
| Alternate Webpage(s) | https://doi.org/10.14445/23488549%2Fijece-v4i3p108 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |