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System Synthesis from AADL using Polychrony
| Content Provider | CiteSeerX |
|---|---|
| Abstract | The increasing system complexity and time to market constraints are great challenges in current electronic system design. Raising the level of abstraction in the design and perform fast yet efficient high-level analysis, validation and synthesis has been widely advocated and considered as a promising solution. Motivated by the same approach, our work on system-level synthesis is presented in this paper: use high-level modeling, domain-specific, language AADL for system-level co-design; use the formal framework Polychrony, based on the synchronous language Signal, for analysis, validation and synthesis. According to Signal’s polychronous model of computation, we propose a model for AADL, which takes both software, hardware and allocation into account. This model enables an early phase timing analysis and synthesis via tools associated with Polychrony. In addition, an example is briefly presented to illustrate our approach. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Early Phase Timing Analysis Efficient High-level Analysis Market Constraint Current Electronic System Design Synchronous Language Signal System-level Synthesis Great Challenge Language Aadl Use High-level Modeling System Synthesis Signal Polychronous Model Formal Framework Polychrony System-level Co-design System Complexity Promising Solution |
| Content Type | Text |
