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Low Power Error Resilient Encoding for on-Chip Data Buses (2002)
| Content Provider | CiteSeerX |
|---|---|
| Author | Bertozzi, Davide Benini, Luca Micheli, Giovanni De |
| Description | As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced effects, etc. Transient delay and logic faults are likely to reduce the reliability of data transfers across datapath bus lines. This paper investigates how to deal with these errors in an energy efficient way. We could opt for error correction, which exhibits larger decoding overhead, or for the retransmission of the incorrectly received data word. Provided the timing penalty associated with this latter technique can be tolerated, we show that retransmission strategies are more effective than correction ones from an energy viewpoint, both for the larger detection capability and for the minor decoding complexity. The analysis was performed by implementing several variants of a Hamming code in the VHDL model of a processor based on the Sparc V8 architecture, and exploiting the characteristics of AMBA bus slave response cycles to carry out retransmissions in a way fully compliant with this standard on-chip bus specification. 1. |
| File Format | |
| Language | English |
| Publisher Date | 2002-01-01 |
| Access Restriction | Open |
| Subject Keyword | Data Word Several Variant Low Power Error Resilient Encoding Error Correction Timing Penalty Sparc V8 Architecture Datapath Bus Line Standard On-chip Bus Specification Response Cycle Deep Submicron Transient Delay Vhdl Model Correction One Power Supply Noise Amba Bus Minor Decoding Complexity Latter Technique Retransmission Strategy Detection Capability Logic Fault On-chip Data Bus Technology Scale Hamming Code Data Transfer Energy Efficient Way On-chip Interconnects Energy Viewpoint |
| Content Type | Text |
| Resource Type | Article |
