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Design methodology for pipelined heterogeneous multiprocessor system (2007).
| Content Provider | CiteSeerX |
|---|---|
| Author | Parameswaran, Sri Shee, Seng Lin |
| Abstract | Multiprocessor SoC systems have led to the increasing use of parallel hardware along with the associated software. These approaches have included coprocessor, homogeneous processor (e.g. SMP) and application specific architectures (i.e. DSP, ASIC). ASIPs have emerged as a viable alternative to conventional processing entities (PEs) due to its configurability and programmability. In this work, we introduce a heterogeneous multi-processor system using ASIPs as processing entities in a pipeline configuration. A streaming application is taken and manually broken into a series of algorithmic stages (each of which make up a stage in a pipeline). We formulate the problem of mapping each algorithmic stage in the system to an ASIP configuration, and propose a heuristic to efficiently search the design space for a pipeline-based multi ASIP system. We have implemented the proposed heterogeneous multiprocessor methodology using a commercial extensible processor (Xtensa LX from Tensilica Inc.). We have evaluated our system by creating two benchmarks (MP3 and JPEG encoders) which are mapped to our proposed design platform. Our multiprocessor design provided a performance improvement of at least 4.11X (JPEG) and 3.36X (MP3) compared to the single processor design. The minimum cost obtained through our heuristic was within 5.47 % and 5.74 % of the best possible values for JPEG and MP3 benchmarks respectively. |
| File Format | |
| Publisher Date | 2007-01-01 |
| Access Restriction | Open |
| Subject Keyword | Xtensa Lx Performance Improvement Design Space Pipelined Heterogeneous Multiprocessor System Homogeneous Processor Minimum Cost Jpeg Encoders Heterogeneous Multiprocessor Methodology Heterogeneous Multi-processor System Parallel Hardware Streaming Application Viable Alternative Design Methodology Multiprocessor Design Possible Value Algorithmic Stage Asip Configuration Commercial Extensible Processor Conventional Processing Entity Tensilica Inc Application Specific Architecture Design Platform Single Processor Design Pipeline-based Multi Asip System Pipeline Configuration Multiprocessor Soc System |
| Content Type | Text |
