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Measuring the quality of a systemc testbench by using code coverage techniques.
| Content Provider | CiteSeerX |
|---|---|
| Author | Peraza, Hernan Große, Daniel Klingauf, Wolfgang Drechsler, Rolf |
| Abstract | The system description language SystemC enables to quickly create executable specifications at adequate levels of abstraction for both hardware/software integration and fast design space exploration. Besides the modeling of a system, verification has become a dominant factor in circuit and system design. Since SystemC is a versatile language based on C++, testbenches at different abstraction levels can easily be built. But the fault coverage of a manually developed testbench is hard to quantify. In this paper, an approach for measuring the quality of SystemC testbenches is presented. The approach is based on dedicated code coverage techniques and identifies all the parts of a SystemC model that have not been tested. Experimental results show the applicability of our methodology. 1. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | System Design Executable Specification System Description Language Systemc Fault Coverage Dedicated Code Coverage Technique Dominant Factor Adequate Level Design Space Exploration Systemc Testbench Developed Testbench Systemc Model Versatile Language Experimental Result Hardware Software Integration Different Abstraction Level Systemc Testbenches Code Coverage Technique |
| Content Type | Text |
