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Guaranteeing hits to improve the efficiency of a small instruction cache.
| Content Provider | CiteSeerX |
|---|---|
| Abstract | Very small instruction caches have been shown to greatly reduce fetch energy. However, for many applications the use of a small filter cache can lead to an unacceptable increase in execution time. In this paper, we propose the Tagless Hit Instruction Cache (TH-IC), a technique for completely eliminating the performance penalty associated with filter caches, as well as a further reduction in energy consumption due to not having to access the tag array on cache hits. Using a few metadata bits per line, we are able to more efficiently track the cache contents and guarantee when hits will occur in our small TH-IC. When a hit is not guaranteed, we can instead fetch directly from the L1 instruction cache, eliminating any additional cycles due to a TH-IC miss. Experimental results show that the overall processor energy consumption can be significantly reduced due to the faster application running time and the elimination of tag comparisons for most of the accesses. 1 |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Fetch Energy Energy Consumption Th-ic Miss Additional Cycle Cache Content Tagless Hit Instruction Cache Execution Time Filter Cache Small Filter Cache Many Application Cache Hit Small Instruction Cache Performance Penalty Metadata Bit Tag Comparison Experimental Result Small Th-ic Overall Processor Energy Consumption L1 Instruction Cache Unacceptable Increase Tag Array |
| Content Type | Text |
