Loading...
Please wait, while we are loading the content...
Implementation of high performance buffer manager for an advance input-queued switch fabric (2002).
| Content Provider | CiteSeerX |
|---|---|
| Author | Lee, Bhum-Cheol Jeong, Gab Joong Lee, Jung-Hee |
| Abstract | In this paper, we describe the implementation of high performance buffer manager that is used in an advanced input-queued switch fabric. It provides the architecture of buffer manager and illustrates the design of ingress and egress buffer for the highspeed switch fabric, which uses a multi-gigabit serial crossbar structure. The designed buffer manager provides wire-speed cell/packet routing with low cost and tolerates the transmission pipeline latency of request and grant data. The buffer manager is implemented in a FPGA chip and supports the speed of OC-48c, 2.5Gbps per port. |
| File Format | |
| Publisher Date | 2002-01-01 |
| Access Restriction | Open |
| Subject Keyword | Multi-gigabit Serial Crossbar Structure Grant Data Egress Buffer Advanced Input-queued Switch Fabric Fpga Chip Wire-speed Cell Packet Highspeed Switch Fabric Advance Input-queued Switch Fabric Low Cost Buffer Manager Transmission Pipeline Latency High Performance Buffer Manager |
| Content Type | Text |
