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Multi-chip multicast schedulers in input-queued switches.
| Content Provider | CiteSeerX |
|---|---|
| Author | Bianco, Andrea Scicchitano, Ra |
| Abstract | Abstract — Multi-chip scheduler implementation in IQ switches are suited to reduce the hardware complexity in very large, high-speed, switches. However, this implies introducing a RTTs (Round Trip Time) among input and output selectors used to determine a matching due to inter-chip latency. This delay requires modifications to scheduling algorithms to allow a fully distributed implementation while keeping good performance. We propose a novel multicast scheduler, named IMRR, an extension of a previously proposed multicast scheduling algorithm named mRRM, making it suitable to a multi-chip implementation, and examine its performance by simulation. I. INTRODUCTION AND RELATED WORK Despite the fact that synchronous slotted IQ (Input-Queued) switches have been proposed as an innovative architecture for high-speed switches many years ago, the interest of the |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Multi-chip Multicast Scheduler Input-queued Switch Good Performance Innovative Architecture High-speed Switch Many Year Introduction Related Work Iq Switch Hardware Complexity Output Selector Novel Multicast Scheduler Inter-chip Latency Abstract Multi-chip Scheduler Implementation Multi-chip Implementation Round Trip Time |
| Content Type | Text |
