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Controlling leakage power with the replacement policy in slumberous caches (2005)
| Content Provider | CiteSeerX |
|---|---|
| Author | Mohyuddin, Nasir Bhatti, Rashed Dubois, Michel |
| Description | As technology scales down at an exponential rate, leakage power is fast becoming the dominant component of the total power budget. A large share of the total leakage power is dissipated in the cache hierarchy. To reduce cache leakage, individual cache lines can be kept in drowsy mode, a low voltage, low leakage state. Every cache access may then result in dynamic power consumption and performance penalties. A trade-off between the amount of leakage power saved on one hand, and the impact on dynamic power and performance on the other hand must be reached. To affect this trade-off, we introduce "slumberous caches " in which the power level of cache lines is controlled with the cache replacement policy. In a slumberous cache, cache lines are maintained at different power save modes which we call "tranquility levels", which depend on their order of replacement priorities. We evaluate the trade-offs in the context of PLRU, a common cache replacement algorithm. We explore various assignments of the tranquility levels to lines and compare overall power and performance impacts. As technology scales down, the dynamic power required to energize slumberous cache lines drops drastically while the leakage power savings remain roughly steady. The performance penalty--in cycles-- remains constant with technology scaling for each scheme we evaluate. |
| File Format | |
| Language | English |
| Publisher | ACM Press |
| Publisher Date | 2005-01-01 |
| Publisher Institution | In CF ’05: Proceedings of the 2nd conference on Computing frontiers |
| Access Restriction | Open |
| Subject Keyword | Performance Impact Large Share Slumberous Cache Line Drop Cache Access Leakage Power Low Voltage Replacement Policy Different Power Save Mode Cache Line Dynamic Power Consumption Cycle Remains Slumberous Cache Cache Leakage Various Assignment Power Level Dominant Component Common Cache Replacement Algorithm Individual Cache Line Exponential Rate Total Power Budget Cache Hierarchy Technology Scale Performance Penalty Tranquility Level Overall Power Replacement Priority Low Leakage State Drowsy Mode Cache Replacement Policy Leakage Power Saving Dynamic Power Total Leakage Power |
| Content Type | Text |
| Resource Type | Article |
