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Drowsy caches: simple techniques for reducing leakage power (2002)
| Content Provider | CiteSeerX |
|---|---|
| Author | Flautner, Krisztián Kim, Nam Sung Martin, Steve Blaauw, David Mudge, Trevor |
| Description | On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink, the dominant component of this power loss will be leakage. However, during a fixed period of time the activity in a cache is only centered on a small subset of the lines. This behavior can be exploited to cut the leakage power of large caches by putting the cold cache lines into a state preserving, low-power drowsy mode. Moving lines into and out of drowsy state incurs a slight performance loss. In this paper we investigate policies and circuit techniques for implementing drowsy caches. We show that with simple architectural techniques, about 80%-90 % of the cache lines in Proceedings of the 29th Annual International Symposium on Computer Architecture |
| File Format | |
| Language | English |
| Publisher Date | 2002-01-01 |
| Access Restriction | Open |
| Subject Keyword | Large Cache Dominant Component On-chip Cache Circuit Technique Drowsy State Leakage Power Small Subset Sizable Fraction State Preserving Power Loss Cache Line Slight Performance Loss Cold Cache Line Simple Technique Total Power Consumption Simple Architectural Technique Power Consumption Drowsy Mode Drowsy Cache Fixed Period |
| Content Type | Text |
| Resource Type | Article |
