NDLI: Power-aware placement

Please wait, while we are loading the content...

Differentiate and deliver: leveraging your partners

Logic soft errors in sub-65nm technologies design and CAD challenges

Variability and energy awareness: a microarchitecture-level perspective

Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages

Automated nonlinear Macromodelling of output buffers for high-speed digital applications

ESL: building the bridge between systems to silicon

Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions

Locality-conscious workload assignment for array-based computations in MPSOC architectures

Response compaction with any number of unknowns using a new LFSR architecture

A green function-based parasitic extraction method for inhomogeneous substrate layers

Partitioning-based approach to fast on-chip decap budgeting and minimization

Temperature-aware resource allocation and binding in high-level synthesis

A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing

Approximate VCCs: a new characterization of multimedia workloads for system-level MpSoC design

Closing the power gap between ASIC and custom: an ASIC perspective

Interconnects are moving from MHz->GHz should you be afraid?: or... "my giga hertz, does yours?"

Design methodology for wireless nodes with printed antennas

An efficient algorithm for statistical minimization of total power under timing yield constraints

Fine-grained application source code profiling for ASIP design

The Titanic: what went wrong!

Wireless platforms: GOPS for cents and MilliWatts

Design methodology for IC manufacturability based on regular logic-bricks

BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition

Operator-based model-order reduction of linear periodically time-varying systems

Cognitive radio techniques for wide area networks

Multiplexer restructuring for FPGA implementation cost reduction

Word level predicate abstraction and refinement for verifying RTL verilog

Automatic generation of customized discrete fourier transform IPs

Power optimal dual-Vdd buffered tree considering buffer stations and blockages

Is methodology the highway out of verification hell?

Full-chip analysis of leakage power under process variations, including spatial correlations

A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3)

Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs

Microarchitecture-aware floorplanning using a statistical design of experiments approach

Matlab extensions for the development, testing and verification of real-time DSP software

Should our power approach be current?

DTM: dynamic tone mapping for backlight scaling

OPERA: optimization with ellipsoidal uncertainty for robust analog IC design

Statistical static timing analysis: how simple can we get?

Formal verification: is it real enough?

TCAM enabled on-chip logic minimization

Power emulation: a new paradigm for power estimation

Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction

Beyond safety: customized SAT-based model checking

BEOL variability and impact on RC extraction

A generic micro-architectural test plan approach for microprocessor verification

Power-aware placement

Minimising buffer requirements of synchronous dataflow graphs with model checking

Path delay test compaction with process variation tolerance

Deterministic approaches to analog performance space exploration (PSE)

Structured/platform ASIC apprentices: which platform will survive your board room?

Quasi-static assignment of voltages and optional cycles for maximizing rewards in real-time systems with energy c-onstraints

Flexible ASIC: shared masking for multiple media processors

Piece-wise approximations of RLCK circuit responses using moment matching

Choosing flows and methodologies for SoC design

SEU tolerant device, circuit and processor design

Energy-effcient physically tagged caches for embedded processors with virtual memory

An effective power mode transition technique in MTCMOS circuits

Systematic development of analog circuit structural macromodels through behavioral model decoupling

Correlation-aware statistical timing analysis with non-gaussian delay distributions

Automatic scenario detection for improved WCET estimation

Multi-frequency wrapper design and optimization for embedded cores under average power constraints

Analysis of full-wave conductor system impedance over substrate using novel integration techniques

Navigating registers in placement for clock network minimization

Leakage power optimization with $dual-V_{th}$ library in high-level synthesis

Simulation models for side-channel information leaks

Modular domain-specific implementation and exploration framework for embedded software platforms

Explaining the gap between ASIC and custom power: a custom perspective

MP core: algorithm and design techniques for efficient channel estimation in wireless applications

Robust gate sizing by geometric programming

Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration

Advanced timing analysis based on post-OPC extraction of critical dimensions

A new canonical form for fast boolean matching in logic synthesis and verification

Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits

MIMO technology for advanced wireless local area networks

FPGA technology mapping: a study of optimality

Structural search for RTL with predicate learning

Race-condition-aware clock skew scheduling

Net weighting to reduce repeater counts during placement

Variations-aware low-power design with voltage scaling

A design platform for 90-nm leakage reduction techniques

A low latency router supporting adaptivity for on-chip interconnects

Timing-driven placement by grid-warping

Matlab as a development environment for FPGA design

Application/architecture power co-optimization for embedded systems powered by renewable sources

A unified optimization framework for equalization filter synthesis

Mapping statistical process variations toward circuit performance variability: an analytical modeling approach

Can we really do without the support of formal methods in the verification of large designs?

Hardware speech recognition for user interfaces in low cost, low power devices

Implementing low-power configurable processors: practical options and tradeoffs

Logic block clustering of large designs for channel-width constrained FPGAs

Efficient SAT solving: beyond supercubes

An effective DFM strategy requires accurate process and IP pre-characterization

IODINE: a tool to automatically infer dynamic invariants for hardware designs

How accurately can we model timing in a placement engine?

Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips

A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs

Mixed signal design space exploration through analog platforms

DC-DC converter-aware power management for battery-operated embedded systems

Device and architecture co-optimization for FPGA power reduction

A quasi-convex optimization approach to parameterized model order reduction

How to determine the necessity for emerging solutions

Hybrid simulation for embedded software energy estimation

A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents

A combined feasibility and performance macromodel for analog circuits

Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model

Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design

N-detection under transparent-scan

Spatially distributed 3D circuit models

Minimizing peak current via opposite-phase clock tree

Incremental exploration of the combined physical and behavioral design space

A pattern matching coprocessor for network security

Simulation based deadlock analysis for system level designs

Keeping hot chips cool

From myth to methodology: cross-layer design for energy-efficient wireless communication

Circuit optimization using statistical static timing analysis

Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse

Self-Compensating Design for Focus Variation

Effective bounding techniques for solving unate and binate covering problems

Scalable trajectory methods for on-demand analog macromodel extraction

RF MEMS in wireless architectures

Incremental retiming for FPGA physical synthesis

Normalization at the arithmetic bit level

A novel synthesis approach for active leakage power reduction using dynamic supply gating

Path based buffer insertion

Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance

A 24 GHz phased-array transmitter in 0.18μm CMOS

Floorplan-aware automated synthesis of bus-based communication architectures

Faster and better global placement by a new transportation algorithm

User-perceived latency driven voltage scaling for interactive applications

Template-driven parasitic-aware optimization of analog integrated circuit layouts

Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxation

Streamline verification process with formal property verification to meet highly compressed design cycle

Improving java virtual machine reliability for memory-constrained embedded systems

Low power network processor design using clock gating

Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility

Prime clauses for fast enumeration of satisfying assignments to boolean circuits

Variation-tolerant circuits: circuit solutions and techniques

VLIW: a case study of parallelism verification

Efficient and accurate gate sizing with piecewise convex delay models

Towards scalable flow and context sensitive pointer analysis

Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 μm and 90 nm technologies

Performance space modeling for hierarchical synthesis of analog integrated circuits

Energy optimal speed control of devices with discrete speed sets

Exploring technology alternatives for nano-scale FPGA interconnects

Structure preserving reduction of frequency-dependent interconnect

Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design

Enhanced leakage reduction Technique by gate replacement

A general framework for accurate statistical timing analysis considering correlations

Dynamic slack reclamation with procrastination scheduling in real-time embedded systems

Secure scan: a design-for-test architecture for crypto chips

DiMES: multilevel fast direct solver based on multipole expansions for parasitic extraction of massively coupled 3D microelectronic structures

A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis

Sign bit reduction encoding for low power applications

High performance encryption cores for 3G networks

Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC

An exact jumper insertion algorithm for antenna effect avoidance/fixing

Trace-driven HW/SW cosimulation using virtual synchronization technique

RADAR: RET-aware detailed routing using fast lithography simulations

Architecture-adaptive range limit windowing for simulated annealing FPGA placement

Exploiting suspected redundancy without proving it

Designing logic circuits for probabilistic computation in the presence of noise

Diffusion-based placement migration

Leakage minimization of nano-scale circuits in the presence of systematic and random variations

FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology

Multilevel full-chip routing for the X-based architecture

System-level energy-efficient dynamic task scheduling

Multi-level approach for integrated spiral inductor optimization

Frequency-based code placement for embedded multiprocessors

A variation tolerant subthreshold design approach

Dynamic abstraction using SAT-based BMC

On the need for statistical timing analysis

StressTest: an automatic approach to test generation via activity monitors

Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method

MiniBit: bit-width optimization via affine arithmetic

Asynchronous circuits transient faults sensitivity evaluation

Optimal procrastinating voltage scheduling for hard real-time systems

Segregation by primary phase factors: a full-wave algorithm for model order reduction

ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction

Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits

A watermarking system for IP protection by a post layout incremental router

Efficient fingerprint-based user authentication for embedded systems

High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trade-offs

Multi-threaded reachability

A lattice-based framework for the classification and design of asynchronous pipelines

Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements

CAD tools for variation tolerance

Smart diagnostics for configurable processor verification

A non-parametric approach for dynamic range estimation of nonlinear systems

Are there economic benefits in DFM?

Power-aware placement

Content Provider	ACM Digital Library
Author	Wang, Qinke Reda, Sherief Kahng, Andrew B. Cheon, Yongseok Ho, Pei-Hsin
Abstract	Lowering power is one of the greatest challenges facing the IC industry today. We present a power-aware placement method that simultaneously performs (1) activity-based register clustering that reduces clock power by placing registers in the same leaf cluster of the clock trees in a smaller area and (2) activity-based net weighting that reduces net switching power by assigning a combination of activity and timing weights to the nets with higher switching rates or more critical timing. The method applies to designs with multiple clocks and gated clocks. We implemented the method and obtained experimental results on 8 real-world designs after placement, routing, extraction and analysis. The power-aware placement method achieved on average 25.3% and 11.4% reduction in net switching power and total power respectively, with 2.0% timing, 1.2% cell area and 11.5% runtime impact. This method has been incorporated into a commercial physical design tool.
Starting Page	795
Ending Page	800
Page Count	6
File Format	PDF
ISBN	1595930582
DOI	10.1145/1065579.1065791
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2005-06-13
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Clock tree Net switching power Dynamic power
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in