NDLI: Optimizing the Operating Voltage of Tunnel FET-Based SRAM Arrays Equipped with Read/Write Assist Circuitry

Please wait, while we are loading the content...

Why Is It So Hard to Make Secure Chips?

Design and Implementation of Real-Time Multi-sensor Vision Systems

Medical Device Security: The First 165 Years

VLSI Design Methods for Low Power Embedded Encryption

High-Speed Polynomial Multiplier Architecture for Ring-LWE Based Public Key Cryptosystems

Area-Efficient Error-Resilient Discrete Fourier Transformation Design using Stochastic Computing

Low Energy Sketching Engines on Many-Core Platform for Big Data Acceleration

A New Methodology for Noise Sensor Placement Based on Association Rule Mining

Real-Time Hardware Stereo Matching Using Guided Image Filter

Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture

Secret Sharing and Multi-user Authentication: From Visual Cryptography to RRAM Circuits

Design of Error-Resilient Logic Gates with Reinforcement Using Implications

A Novel On-Chip Impedance Calibration Method for LPDDR4 Interface between DRAM and AP/SoC

Polynomial Arithmetic Using Sequential Stochastic Logic

VarDroid: Online Variability Emulation in Android/Linux Platforms

Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM

Trellis-search based Dynamic Multi-Path Connection Allocation for TDM-NoCs

Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges

FCM: Towards Fine-Grained GPU Power Management for Closed Source Mobile Games

Exploring Main Memory Design Based on Racetrack Memory Technology

Approximate Differential Encoding for Energy-Efficient Serial Communication

Reduced Overhead Gate Level Logic Encryption

Concurrent Error Detection for Reliable SHA-3 Design

Low-Power Manycore Accelerator for Personalized Biomedical Applications

MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router

Computing Complex Functions using Factorization in Unipolar Stochastic Logic

A Metastability Immune Timing Error Masking Flip-Flop for Dynamic Variation Tolerance

Defense Systems and IoT: Security Issues in an Era of Distributed Command and Control

Reducing Soft-error Vulnerability of Caches using Data Compression

A General Sign Bit Error Correction Scheme for Approximate Adders

Ultra-Robust Null Convention Logic Circuit with Emerging Domain Wall Devices

Neural Network-based Prediction Algorithms for In-Door Multi-Source Energy Harvesting System for Non-Volatile Processors

Enhancing Hardware Security with Emerging Transistor Technologies

Prolonging Lifetime of Non-volatile Last Level Caches with Cluster Mapping

Quality of Service-Aware, Scalable Cache Tuning Algorithm in Consumer-based Embedded Devices

An Offline Frequent Value Encoding for Energy-Efficient MLC/TLC Non-volatile Memories

Fast Thermal Simulation using SystemC-AMS

A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register File

Secure Model Checkers for Network-on-Chip (NoC) Architectures

Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs

Modular Placement for Interposer based Multi-FPGA Systems

DCC: Double Capacity Cache Architecture for Narrow-Width Values

Exploring Configurable Non-Volatile Memory-based Caches for Energy-Efficient Embedded Systems

Security Meets Nanoelectronics for Internet of Things Applications

Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation

RRAM Refresh Circuit: A Proposed Solution To Resolve The Soft-Error Failures For $HfO_{2}/Hf$ 1T1R RRAM Memory Cell

Inter-Tier Crosstalk Noise On Power Delivery Networks For 3-D ICs With Inductively-Coupled Interconnects

A Unified Model of Power Sources for the Simulation of Electrical Energy Systems

The Applications of NVM Technology in Hardware Security

A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors

Temperature-aware Dynamic Voltage Scaling for Near-Threshold Computing

Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices

Learning-Based Near-Optimal Area-Power Trade-offs in Hardware Design for Neural Signal Acquisition

A Clockless Sequential PUF with Autonomous Majority Voting

Parameter-importance based Monte-Carlo Technique for Variation-aware Analog Yield Optimization

Real-Time Analysis for Wormhole NoC: Revisited and Revised

A Parallel Random Walk Solver for the Capacitance Calculation Problem in Touchscreen Design

Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques

Multiple Attempt Write Strategy for Low Energy STT-RAM

Tracking Data Flow at Gate-Level through Structural Checking

Enhancing Fault Emulation of Transient Faults by Separating Combinational and Sequential Fault Propagation

Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICs

Delay Estimates for Graphene Nanoribbons: A Novel Measure of Fidelity and Experiments with Global Routing Trees

Hardware-Accelerated Software Library Drivers Generation for IP-Centric SoC Designs

Survey of Emerging Technology Based Physical Unclonable Funtions

Dynamic Real-Time Scheduler for Large-Scale MPSoCs

Leakage Power Minimization in Deep Sub-Micron Technology by Exploiting Positive Slacks of Dependent Paths

Optimizing the Operating Voltage of Tunnel FET-Based SRAM Arrays Equipped with Read/Write Assist Circuitry

Load Balanced On-Chip Power Delivery for Average Current Demand

Asynchronous High Speed Serial Links Analysis using Integrated Charge for Event Detection

8T1R: A Novel Low-power High-speed RRAM-based Non-volatile SRAM Design

Extracting Designs of Secure IPs Using FPGA CAD Tools

An Enhanced Analytical Electrical Masking Model for Multiple Event Transients

Design and Comparative Evaluation of a Hybrid Cache Memory at Architectural Level

Capturing True Workload Dependency of BTI-induced Degradation in CPU Components

A Sampling Clock Skew Correction Technique for Time-Interleaved SAR ADCs

Performance Constraint-Aware Task Mapping to Optimize Lifetime Reliability of Manycore Systems

Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers

ASIC Implementation of An All-digital Self-adaptive PVTA Variation-aware Clock Generation System

Task-Resource Co-Allocation for Hotspot Minimization in Heterogeneous Many-Core NoCs

Ultra-Low Energy Reconfigurable Spintronic Threshold Logic Gate

Guiding Power/Quality Exploration for Communication-Intense Stream Processing

Red-Shield: Shielding Read Disturbance for STT-RAM Based Register Files on GPUs

Modeling and Study of Two-BDT-Nanostructure based Sequential Logic Circuits

Optimizing the Operating Voltage of Tunnel FET-Based SRAM Arrays Equipped with Read/Write Assist Circuitry

Content Provider	ACM Digital Library
Author	Shafaei, Alireza Pedram, Massoud Afzali-Kusha, Hassan
Abstract	This paper deals with obtaining the minimum operating voltage of memory arrays based on TFET SRAM cells. First, we compare the I-V characteristics of two TFETs and one FDSOI using SPICE simulations based on 20nm technology models. The results reveal that TFET devices exhibit high ON/OFF current ratios at different power supply voltage levels. This observation suggests a higher stability for SRAM cells based on these devices. Next, the characteristics of 6T SRAM cells implemented using minimum sized transistors based on these three device structures are compared. The comparison, which considers two TFET cell structures, i.e., inward and outward SRAMs, is performed at different supply voltages. The results for the hold static noise margin show that at low supply voltages (i.e., below 300mV), the FDSOI SRAM cell cannot hold data whereas both the inward and outward structures of TFET have acceptable noise margins at all supply voltages. Among the two TFET structures, the outward cell is selected because of higher speed especially for the write operation. TFET SRAMs suffer from long read access latency at ultra-low supply voltages (e.g., 150mV). The problem, however, may be overcome by using the negative GND read-assist technique. The results show that for a 32×32 TFET outward SRAM array, the minimum energy consumption (energy-delay product) may be achieved at the supply voltage of 200mV (300mV) with 1.32GHz (4.55GHz) as the read access frequency.
Starting Page	415
Ending Page	420
Page Count	6
File Format	PDF
ISBN	9781450342742
DOI	10.1145/2902961.2903031
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-05-18
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Fdsoi Tfet Negative gnd technique Read and write assist techniques Sram cells
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in