NDLI: Best ways to use billions of devices on a wireless mobile SoC

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A brand new wireless day

Variability-driven module selection with joint design time optimization and post-silicon tuning

Predictive power aware management for embedded mobile devices

Reconfigurable RTD-based circuit elements of complete logic functionality

A 1.2GHz delayed clock generator for high-speed microprocessors

Global optimization of common subexpressions for multiplierless synthesis of multiple constant multiplications

Efficient numerical modeling of random rough surface effects for interconnect internal impedance extraction

Symmetry-aware placement with transitive closure graphs for analog layout design

Predictive models and CAD methodology for pattern dependent variability

MaizeRouter: engineering an effective global router

Interconnect modeling for improved system-level design optimization

Floating-point reconfiguration array processor for 3D graphics physics engine

The evolution of SoC platform according to the new mobile paradigm

Statistical gate delay model for multiple input switching

Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm

DPlace2.0: a stable and efficient analytical placement based on diffusion

In-band mobile digital TV transmission technology for advanced television systems committee

Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof

Hybrid solid-state disks: combining heterogeneous NAND flash in large SSDs

Architecture-level thermal behavioral characterization for multi-core microprocessors

Are system level EDA tools/methodologies coming?

Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering

Determination of optimal polynomial regression function to decompose on-die systematic and random variations

Reliability-aware design for nanometer-scale devices

The future of semiconductor industry: a foundry's perspective

Soft error rate reduction using redundancy addition and removal

Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches

A unified methodology for power supply noise reduction in modern microarchitecture design

Concurrent SoC and SiP designs

Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits

ReSP: a non-intrusive transaction-level reflective MPSoC simulation platform for design space exploration

Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension

Reaching the limits of low power design

An efficient, fully nonlinear, variability-aware non-Monte-Carlo yield estimation procedure with applications to SRAM cells and ring oscillators

SPKM: a novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures

Best ways to use billions of devices on a chip: panel

Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA

A dynamic-programming algorithm for reducing the energy consumption of pipelined system-level streaming applications

MBARC: a scalable memory based reconfigurable computing framework for nanoscale devices

LVDS-type on-chip transmision line interconnect with passive equalizers in 90 nm CMOS process

Decomposition based approach for synthesis of multi-level threshold logic circuits

Efficient techniques for 3-D impedance extraction using mixed boundary element method

Constraint-free analog placement with topological symmetry structure

Technology modeling and characterization beyond the 45nm node

A new global router for modern designs

NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks

Super-K: a SoC for single-chip ultra mobile computer

Non-Gaussian statistical timing models of die-to-die and within-die parameter variations for full chip analysis

Block cache for embedded systems

Total power optimization combining placement, sizing and multi-Vt through slack distribution management

In-vehicle vision processors for driver assistance systems

A symbolic approach for mixed-signal model checking

Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information

Full-chip thermal analysis for the early design stage via generalized integral transforms

A fast incremental clock skew scheduling algorithm for slack optimization

Within-die process variations: how accurately can they be statistically modeled?

An industrial perspective of power-aware reliable SoC design

Localized random access scan: towards low area and routing overhead

Automatic interface synthesis based on the classification of interface protocols of IPs

Heuristic power/ground network and floorplan co-design method

A new low energy BIST using a statistical code

Collaborative hardware/software partition of coarse-grained reconfigurable system using evolutionary ant colony optimization

Exploring power management in multi-core systems

Software-cooperative power-efficient heterogeneous multi-core for media processing

Analog circuit simulation using range arithmetics

Block remap with turnoff: a variation-tolerant cache design technique

VEBoC: variation and error-aware design for billions of devices on a chip

A multicycle communication architecture and synthesis flow for global interconnect resource sharing

Temperature-aware MPSoC scheduling for reducing hot spots and gradients

Moving forward: a non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms

A slew-rate controlled output driver with one-cycle tuning time

Timing-power optimization for mixed-radix ling adders by integer linear programming

Generating stable and sparse reluctance/inductance matrix under insufficient conditions

TCG-based multi-bend bus driven floorplanning

Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond

Routability driven modification method of monotonic via assignment for 2-layer ball grid array packages

Automatic generation of hardware dependent software for MPSoCs from abstract system specifications

Non-Gaussian statistical timing analysis using second-order polynomial fitting

A compiler-in-the-loop framework to explore horizontally partitioned cache architectures

An innovative Steiner tree based approach for polygon partitioning

Multi-core DSP for base stations: large and small

Faster projection based methods for circuit level verification

Automatic re-coding of reference code into structured and analyzable SoC models

A stochastic local hot spot alerting technique

Clock tree synthesis with data-path sensitivity matching

Chebyshev affine arithmetic based parametric yield prediction under limited descriptions of uncertainty

A design-for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults

The shining embedded system design methodology based on self dynamic reconfigurable architectures

Vertical via design techniques for multi-layered P/G networks

On reducing both shift and capture power for scan-based testing

Design space exploration for a coarse grain accelerator

Dependability, power, and performance trade-off on a multicore processor

Experiences of low power design implementation and verification

LTCC spiral inductor modeling, synthesis, and optimization

ORB: an on-chip optical ring bus communication architecture for multi-processor systems-on-chip

Quo vadis, BTSoC (billion transistor SoC)?

Scheduling with integer time budgeting for low-power optimization

Run-time power gating of on-chip routers using look-ahead routing

A CAD tool for RF MEMS devices

A low-leakage current power 180-nm CMOS SRAM

Efficient synthesis of compressor trees on FPGAs

Hierarchical Krylov subspace reduced order modeling of large RLC circuits

Large-scale fixed-outline floorplanning design using convex optimization techniques

Ordered escape routing based on Boolean satisfiability

Application-specific network-on-chip architecture synthesis based on set partitions and Steiner trees

A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application

Fast, quasi-optimal, and pipelined instruction-set extensions

An MILP-based wire spreading algorithm for PSM-aware layout modification

1-cc computer using UWB-IR for wireless sensor network

A debug probe for concurrently debugging multiple embedded cores and inter-core transactions in NoC-based systems

Action coverage formulation for power optimization in body sensor networks

Design rule optimization of regular layout for leakage reduction in nanoscale design

Buffered clock tree synthesis for 3D ICs under thermal variations

Distribution arithmetic for stochastical analysis

GECOM: test data compression combined with all unknown response masking

Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival

Statistical mixed $V_{t}$ allocation of body-biased circuits for reduced leakage variation

Robust test generation for power supply noise induced path delay faults

Efficient symbolic multi-objective design space exploration

High performance current-mode differential logic

Low power architecture and design techniques for mobile handset LSI Medity™ M2

Symmetry constraint based on mismatch analysis for analog layout in SOI technology

Webpage-based benchmarks for mobile device design

Best ways to use billions of devices on a wireless mobile SoC

REWIRED: REgister Write Inhibition by REsource Dedication

Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures

A CMOS direct sampling mixer using switched capacitor filter technique for software-defined radio

Area recovery under depth constraint by cut substitution for technology mapping for LUT-based FPGAs

Statistical noise margin estimation for sub-threshold combinational circuits

Bus-aware microarchitectural floorplanning

MeshWorks: an efficient framework for planning, synthesis and optimization of clock mesh networks

Static timing: back to our roots

Load scheduling: reducing pressure on distributed register files for free

Low power clock buffer planning methodology in F-D placement for large scale circuit design

A fast two-pass HDL simulation with on-demand dump

Dynamic scheduling of imprecise-computation tasks in maximizing QoS under energy constraints for embedded systems

Investigation of diffusion rounding for post-lithography analysis

A delay model for interconnect trees based on ABCD matrix

Handling partial correlations in yield prediction

A multi-processor NoC platform applied on the 802.11i TKIP cryptosystem

Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching

Test vector chains for increased targeted and untargeted fault coverage

Scalable unified dual-radix architecture for montgomery multiplication in GF(P) and $GF(2^{n})$

NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?

Best ways to use billions of devices on a chip: error predictive, defect tolerant and error recovery designs

An efficient performance improvement method utilizing specialized functional units in behavioral synthesis

Statistical power profile correlation for realistic thermal estimation

Small-area CMOS RF distributed mixer using multi-port inductors

An optimal algorithm for sizing sequential circuits for industrial library based designs

LP based white space redistribution for thermal via planning and performance optimization in 3D ICs

Power grid analysis benchmarks

Analytical model for the impact of multiple input switching noise on timing

Parallel fault backtracing for calculation of fault coverage

Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification

Duo-binary circular turbo decoder based on border metric encoding for WiMAX

Area and power efficient design of coarse time synchronizer and frequency offset estimator for fixed WiMAX systems

A low-cost cryptographic processor for security embedded system

Multithreaded coprocessor interface for multi-core multimedia SoC

Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP processor

Best ways to use billions of devices on a wireless mobile SoC

Content Provider	ACM Digital Library
Author	Kim, KyungHo
Abstract	A rapid growth in the field of Information Technologies (IT) over the last decade gave us unimaginable possibilities and lots of convenience in our life, i.e. highspeed Internet, mobile-TV, High-definition digital TV, 3D-gaming, mobile multimedia player, Ultra-Mobile PC and so on. Nowadays, the technology is even exceeding market demands. Apple produced 160GB iPod which stores 40,000 songs. Samsung showed a world-first mobile phone with 10Megapixel camera on it. HSDPA-based video telephony service was commercialized in Korea. In near future, a CMOS integration technology will enable us to put a billion of transistors on a single chip. This is a great opportunity undoubtedly, but it can be also a hazard to IDM or fabless companies. Recently major IDM companies have chosen to take fab-lite model and foundry joint-development programs because of skyrocketing expenses of nanometer processes development [1]. As the SoC NRE cost also increases exponentially with the system complexity, a single failure in a product or a project can bring an unrecoverable damage to the company. Therefore a market-oriented and market-driven approach should be taken rather than a technology-oriented or product-driven approach. In the approach, a SoC development project must be kicked off by surveying market requirements first. In the wireless handset market for example, there are customers' requirements such as (1) wireless broadband access, (2) ubiquitous connectivity, (3) less frequent battery recharging, (4) stylish look, and (5) low-cost hardware. These requirements can be translated into more technical and engineering terms as shown in second row of the following table. These requirements bring up Modem SoC design issues such as high-speed protocol processing, programmability and reconfigurable hardware for multistandard support, system-level low-power design, and system integration issues. These design challenges are more crucial in a wireless SoC market rather than the ultra-high-density integration issues. In this panel discussion, we will discuss the various solutions to deal with these wireless SoC design issues and their solutions as elaborated in the last row of the table. These solutions will finally lead us to the best way to use billions of devices on a chip.
Starting Page	810
Ending Page	810
Page Count	1
File Format	PDF
ISBN	9781424419227
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-01-21
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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