NDLI: Best ways to use billions of devices on a chip: panel

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A brand new wireless day

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Global optimization of common subexpressions for multiplierless synthesis of multiple constant multiplications

Efficient numerical modeling of random rough surface effects for interconnect internal impedance extraction

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Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches

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Best ways to use billions of devices on a chip: panel

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Full-chip thermal analysis for the early design stage via generalized integral transforms

A fast incremental clock skew scheduling algorithm for slack optimization

Within-die process variations: how accurately can they be statistically modeled?

An industrial perspective of power-aware reliable SoC design

Localized random access scan: towards low area and routing overhead

Automatic interface synthesis based on the classification of interface protocols of IPs

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Temperature-aware MPSoC scheduling for reducing hot spots and gradients

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Timing-power optimization for mixed-radix ling adders by integer linear programming

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TCG-based multi-bend bus driven floorplanning

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Automatic generation of hardware dependent software for MPSoCs from abstract system specifications

Non-Gaussian statistical timing analysis using second-order polynomial fitting

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An innovative Steiner tree based approach for polygon partitioning

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Automatic re-coding of reference code into structured and analyzable SoC models

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Clock tree synthesis with data-path sensitivity matching

Chebyshev affine arithmetic based parametric yield prediction under limited descriptions of uncertainty

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Hierarchical Krylov subspace reduced order modeling of large RLC circuits

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Ordered escape routing based on Boolean satisfiability

Application-specific network-on-chip architecture synthesis based on set partitions and Steiner trees

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Fast, quasi-optimal, and pipelined instruction-set extensions

An MILP-based wire spreading algorithm for PSM-aware layout modification

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Action coverage formulation for power optimization in body sensor networks

Design rule optimization of regular layout for leakage reduction in nanoscale design

Buffered clock tree synthesis for 3D ICs under thermal variations

Distribution arithmetic for stochastical analysis

GECOM: test data compression combined with all unknown response masking

Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival

Statistical mixed $V_{t}$ allocation of body-biased circuits for reduced leakage variation

Robust test generation for power supply noise induced path delay faults

Efficient symbolic multi-objective design space exploration

High performance current-mode differential logic

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Symmetry constraint based on mismatch analysis for analog layout in SOI technology

Webpage-based benchmarks for mobile device design

Best ways to use billions of devices on a wireless mobile SoC

REWIRED: REgister Write Inhibition by REsource Dedication

Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures

A CMOS direct sampling mixer using switched capacitor filter technique for software-defined radio

Area recovery under depth constraint by cut substitution for technology mapping for LUT-based FPGAs

Statistical noise margin estimation for sub-threshold combinational circuits

Bus-aware microarchitectural floorplanning

MeshWorks: an efficient framework for planning, synthesis and optimization of clock mesh networks

Static timing: back to our roots

Load scheduling: reducing pressure on distributed register files for free

Low power clock buffer planning methodology in F-D placement for large scale circuit design

A fast two-pass HDL simulation with on-demand dump

Dynamic scheduling of imprecise-computation tasks in maximizing QoS under energy constraints for embedded systems

Investigation of diffusion rounding for post-lithography analysis

A delay model for interconnect trees based on ABCD matrix

Handling partial correlations in yield prediction

A multi-processor NoC platform applied on the 802.11i TKIP cryptosystem

Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching

Test vector chains for increased targeted and untargeted fault coverage

Scalable unified dual-radix architecture for montgomery multiplication in GF(P) and $GF(2^{n})$

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Statistical power profile correlation for realistic thermal estimation

Small-area CMOS RF distributed mixer using multi-port inductors

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LP based white space redistribution for thermal via planning and performance optimization in 3D ICs

Power grid analysis benchmarks

Analytical model for the impact of multiple input switching noise on timing

Parallel fault backtracing for calculation of fault coverage

Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification

Duo-binary circular turbo decoder based on border metric encoding for WiMAX

Area and power efficient design of coarse time synchronizer and frequency offset estimator for fixed WiMAX systems

A low-cost cryptographic processor for security embedded system

Multithreaded coprocessor interface for multi-core multimedia SoC

Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP processor

Best ways to use billions of devices on a chip: panel

Content Provider	ACM Digital Library
Author	Martin, Grant Dutt, Nikil Kim, KyungHo Kobayashi, Kazutoshi Chen, Deming Henkel, Joerg
Abstract	We all know that Moore's law is good for at least a few more generations of silicon process, and this will give rise to many integrated circuits having billions of transistors on them. The leading 45 nm processors being announced are getting close to a billion transistors as of 2007. But how can we best use these devices in the future? Integrating more and more features and functions onto SoCs may not be the optimal use for all of these billions of resources. Indeed, to even have a working device at 45, 32, 22 and 16 nm may require new architectures and new structures to be incorporated. Among the many ideas that can be advanced to best use the 'billions and billions served' are: - multicore and multiprocessor systems - yet more memory, to hold the embedded software and data required by multiprocessor architectures - more and more elaborate on-chip interconnect and network structures - redundant structures for defect tolerance - structures and architectures for dynamic error recovery - a variety of schemes to allow lower and lower power and energy consumption At the same time, billions of transistors on a chip will pose increasing challenges to our design methodologies, integration approaches and design tools. How can we best conceive of, architect, design, integrate, verify and manufacture such devices? This panel draws on several academic and industry experts who will discuss their views on the best things to integrate into future ICs, and the best ways to do that integration. It will give an excellent opportunity to the audience to challenge and discuss these ideas and to advocate their own views. As well as considering the 'best' ways to use these resources, the panel will also be a good opportunity to discuss the 'worst' ways to proceed. What architectural dead-ends should be avoided as we move through each silicon process generation?.
Starting Page	801
Ending Page	802
Page Count	2
File Format	PDF
ISBN	9781424419227
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-01-21
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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