NDLI: Efficient parallel power grid analysis via additive Schwarz method

Please wait, while we are loading the content...

Online fault detection and tolerance for photovoltaic energy harvesting systems

Spatial correlation modeling for probe test cost reduction in RF devices

Layout small-angle rotation and shift for EUV defect mitigation

Improving last level cache locality by integrating loop and data transformations

Bridging pre- and post-silicon debugging with BiPeD

TRIAD: a triple patterning lithography aware detailed router

Noise based logic: why noise?

On the computation of criticality in statistical timing analysis

Scalable sampling methodology for logic simulation: reduced-ordered Monte Carlo

Impact of range and precision in technology on cell-based design

Dealing with IC manufacturability in extreme scaling

Stability assurance and design optimization of large power delivery networks with multiple on-chip voltage regulators

Scaling the "memory wall"

Progress and challenges in VLSI placement research

Modeling and design automation of biological circuits and systems

CACTI-IO: CACTI with off-chip power-area-timing models

A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations

Opening: introduction to CAD contest at ICCAD 2012

System energy consumption is a multi-player game

Voltage-aware chip-level design for reliability-driven pin-constrained EWOD chips

Fast transform-based preconditioners for large-scale power grid analysis on massively parallel architectures

An efficient control variates method for yield estimation of analog circuits based on a local model

Toward codesign in high performance computing systems

Accurate on-chip router area modeling with kriging methodology

Multiple tunable constant multiplications: algorithms and applications

Confronting and exploiting operating environment uncertainty in predictive analysis of signal integrity

ISBA: an independent set-based algorithm for automated partial reconfiguration module generation

Implementing high-performance, low-power embedded processors: challenges and solutions

Multi-level cell STT-RAM: is it realistic or just a dream?

Challenges in post-silicon validation of high-speed I/O links

Functional post-silicon diagnosis and debug for networks-on-chip

Simultaneous information flow security and circuit redundancy in Boolean gates

Performance-driven analog placement considering monotonic current paths

2012 TAU power grid simulation contest: benchmark suite and results

Transistor technologies and pixel circuit design for efficient active-matrix organic light-emitting diode displays

Clock mesh synthesis with gated local trees and activity driven register clustering

A thermal and process variation aware MTJ switching model and its applications in soft error analysis

High-performance, low-power resonant clocking

Tunable sensors for process-aware voltage scaling

Small-delay-fault ATPG with waveform accuracy

A methodology for the early exploration of design rules for multiple-patterning technologies

Asymmetric DRAM synthesis for heterogeneous chip multiprocessors in 3D-stacked architecture

Novel test detection to improve simulation efficiency: a commercial experiment

Maze routing algorithms with exact matching constraints for analog and mixed signal designs

An efficient implementation of numerical integration using logical computation on stochastic bit streams

A dynamic method for efficient random mismatch characterization of standard cells

Trajectory-directed discrete state space modeling for formal verification of nonlinear analog circuits

An efficient algorithm for library-based cell-type selection in high-performance low-power designs

Circuit reliability: from physics to architectures

A silicon-validated methodology for power delivery modeling and simulation

Test challenges in designing complex 3D chips: what is on the horizon for EDA industry?

Placement: hot or not?

AFReP: application-guided function-level registerfile power-gating for embedded processors

Electromigration-aware routing for 3D ICs with stress-aware EM modeling

ICCAD-2012 CAD contest in finding the minimal logic difference for functional ECO and benchmark suite

Compiling program control flows into biochemical reactions

Deterministic random walk preconditioning for power grid analysis

A fast time-domain EM-TCAD coupled simulation framework via matrix exponential

Distributed memory interface synthesis for network-on-chips with 3D-stacked DRAMs

The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic

Multi-scale, multi-physics analysis for device, chip, package, and board level

Fine-grained hardware/software methodology for process migration in MPSoCs

Latency tolerance for throughput computing

Ultra-low power NEMS FPGA

Post-silicon performance modeling and tuning of analog/mixed-signal circuits via Bayesian model fusion

TRACKER: a low overhead adaptive NoC router with load balancing selection strategy

On logic synthesis for timing speculation

Configurable analog routing methodology via technology and design constraint unification

PGT_SOLVER: an efficient solver for power grid transient analysis

Battery cell configuration for organic light emitting diode display in modern smartphones and tablet-PCs

Fast approximation for peak power driven voltage partitioning in almost linear time

Modeling and synthesis of quality-energy optimal approximate adders

Collaborative calibration of on-chip thermal sensors using performance counters

Experimental analysis of a ring oscillator network for hardware trojan detection in a 90nm ASIC

A polynomial time triple patterning algorithm for cell based row-structure layout

Optimizing bandwidth and power of graphics memory with hybrid memory technologies and adaptive data migration

A robust general constrained random pattern generator for constraints with variable ordering

Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree construction

Utilizing random noise in cryptography: where is the tofu?

Classifying circuit performance using active-learning guided support vector machines

Word level feature discovery to enhance quality of assertion mining

Sensitivity-guided metaheuristics for accurate discrete gate sizing

Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications

3D integrated circuits: designing in a new dimension

Efficient multiple-bit retention register assignment for power gated design: concept and algorithms

3D transient thermal solver using non-conformal domain decomposition approach

ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite

Dictionary-based error recovery in cyberphysical digital-microfluidic biochips

Efficient parallel power grid analysis via additive Schwarz method

GPSCP: a general-purpose support-circuit preconditioning approach to large-scale SPICE-accurate nonlinear circuit simulations

Efficient design space exploration for component-based system design

Memory partitioning and scheduling co-optimization in behavioral synthesis

Design strategies for high-dimensional electromagnetic systems

Active compensation technique for the thin-film transistor variations and OLED aging of mobile device displays

Ultra high density logic designs using transistor-level monolithic 3D integration

Validation signature testing: a methodology for post-silicon validation of analog/mixed-signal circuits

Provably complete hardware trojan detection using test point insertion

Lazy man's logic synthesis

Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion

PowerRush: efficient transient simulation for power grid analysis

Mobile devices user: the subscriber and also the publisher of real-time OLED display power management plan

Multiobjective optimization of deadspace, a critical resource for 3D-IC integration

Representative critical reliability paths for low-cost and accurate on-chip aging evaluation

Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches

Fast and scalable hybrid functional verification and debug with dynamically reconfigurable co-simulation

Construction of rectilinear Steiner minimum trees with slew constraints over obstacles

Learning from biological neurons to compute with electronic noise

ICCAD-2012 CAD contest in fuzzy pattern matching for physical verification and benchmark suite

Reactant minimization during sample preparation on digital microfluidic biochips using skewed mixing trees

Circuit simulation via matrix exponential method for stiffness handling and parallel processing

Verifying dynamic properties of nonlinear mixed-signal circuits via efficient SMT-based techniques

Co-simulations of electromagnetic and thermal effects in electronic circuits using non-conformal numerical methods

Using standardized quantization for multi-party PPUF matching: foundations and applications

Minimizing area and power of sequential CMOS circuits using threshold decomposition

Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits

Parallel forward and back substitution for efficient power grid simulation

A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing

Design analysis of IC power delivery

Power grid effects and their impact on-die

Overview of vectorless/early power grid verification

Efficient parallel power grid analysis via additive Schwarz method

Content Provider	ACM Digital Library
Author	Yu, Ting Wong, Martin D. F. Xiao, Zigang
Abstract	Due to the rapid advances of integrated circuit technology, the size of power distribution network (power grid) is becoming larger and larger. There are usually multi-million nodes on a power grid. Analyzing these huge power grids has become very expensive in terms of both time and memory. This paper presents an efficient parallel implementation of the Additive Schwarz Method (ASM) for IR-drop analysis of large-scale power grid. Based on distributed memory system, a new data storage method is proposed to overcome memory bottleneck of traditional methods. Techniques including overlapping in multiple layer and irregular power grid, via detection and grouping are utilized to accelerate the simulation. Moreover, a new communication strategy exhibiting minimum communication overhead is proposed. The proposed method is very accurate in the final solution, with the maximum error less than 0.1mv. Experimental results on industrial medium size benchmarks show that the proposed method achieves more than 110X speedup over a state-of-the-art direct LU solver. The proposed approach can easily solve very large-scale benchmarks, while LU solver fails to obtain the solution because of system memory limitation. It is the first time reported in literature that IR-drop analysis of power grid with over 190M nodes is successfully solved within 5 minutes.
Starting Page	399
Ending Page	406
Page Count	8
File Format	PDF
ISBN	9781450315739
DOI	10.1145/2429384.2429468
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-11-05
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in