NDLI: Tunable sensors for process-aware voltage scaling

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Tunable sensors for process-aware voltage scaling

Content Provider	ACM Digital Library
Author	Kahng, Andrew B. Chan, Tuck-Boon
Abstract	VLSI circuits usually allocate excess margin to account for worst-case process variation. Since most chips are fabricated at process conditions better than the worst-case corner, adaptive voltage scaling (AVS) is commonly used to reduce power consumption whenever possible. A typical AVS setup relies on a performance monitor that replicates critical paths of the circuit to guide voltage scaling. However, it is difficult to define appropriate critical paths for an SoC which has multiple operating modes and IPs. In this paper, we propose a different methodology for AVS which matches the voltage scaling characteristics of a circuit rather than the delays of critical paths. This fundamental change in monitoring strategy simplifies the monitoring circuitry as well as the calibration flow of conventional monitoring methods. To enable the proposed methodology, we study voltage scaling characteristics of digital circuits. Based on our analyses, we develop design guidelines as well as design monitoring circuits which have tunable voltage scaling characteristics. Our experimental results show that this methodology can be used for AVS with a simplified calibration flow.
Starting Page	7
Ending Page	14
Page Count	8
File Format	PDF
ISBN	9781450315739
DOI	10.1145/2429384.2429387
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-11-05
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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