NDLI: Low power SRAM techniques for handheld products

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FinFET-based SRAM design

Instruction packing: reducing power and delay of the dynamic scheduling logic

A 120nm low power asynchronous ADC

Challenges and opportunities for low power FPGAs in nanometer technologies

A GHz-class charge recovery logic

An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs

A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations

An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design

Complexity reduction in an nRERL microprocessor

An evaluation of code and data optimizations in the context of disk power reduction

Power grid voltage integrity verification

Hierarchical power management with application to scheduling

Design and optimization on dynamic power system for self-powered integrated wireless sensing nodes

A tunable bus encoder for off-chip data buses

PARE: a power-aware hardware data prefetching engine

Replacing global wires with an on-chip network: a power analysis

Technology and design challenges for mobile communication and computing products

Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits

Energy-efficient and high-performance instruction fetch using a block-aware ISA

A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13μm CMOS

Low-power fanout optimization using multiple threshold voltage inverters

Cascaded carry-select adder $(C^{2}SA):$ a new structure for low-power CSA design

Power-optimal repeater insertion considering Vdd and Vth as design freedoms

Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications

Driver pre-emphasis techniques for on-chip global buses

Optimizing sensor movement planning for energy efficiency

The need for a full-chip and package thermal model for thermally optimized IC designs

Runtime identification of microprocessor energy saving opportunities

Accurate battery lifetime estimation using high-frequency power profile emulation

Fast configurable-cache tuning with a unified second-level cache

Snug set-associative caches: reducing leakage power while improving performance

A low-power crossroad switch architecture and its core placement for network-on-chip

Wearable computing: a catalyst for business and entertainment

Effectiveness of low power $dual-V_{t}$ designs in nano-scale technologies under process parameter variations

Energy-aware fetch mechanism: trace cache and BTB customization

A low power current steering digital to analog converter in 0.18 Micron CMOS

A low-power bus design using joint repeater insertion and coding

Region-level approximate computation reuse for power reduction in multimedia applications

Probabilistic dual-Vth leakage optimization under variability

Two efficient methods to reduce power and testing time

Multi-story power delivery for supply noise reduction and low voltage operation

Power prediction for intel XScale® processors using performance monitoring unit events

Peak temperature control and leakage reduction during binding in high level synthesis

Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy

On-chip digital power supply control for system-on-chip applications

Dataflow analysis for energy-efficient scratch-pad memory management

An energy efficient TLB design methodology

System level power and performance modeling of GALS point-to-point communication interfaces

Analysis and mitigation of variability in subthreshold design

Understanding the energy efficiency of SMT and CMP with multiclustering

Systematic power reduction and performance analysis of mismatch limited ADC designs

An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS

Joint exploration of architectural and physical design spaces with thermal consideration

Linear programming for sizing, $V_{th}$ and $V_{dd}$ assignment

Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices

Low power SRAM techniques for handheld products

Power reduction by varying sampling rate

LAP: a logic activity packing methodology for leakage power-tolerant FPGAs

Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation

Self-timed circuits for energy harvesting AC power supplies

Energy reduction in multiprocessor systems using transactional memory

Synonymous address compaction for energy reduction in data TLB

A technique for low energy mapping and routing in network-on-chip architectures

Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage

A simple mechanism to adapt leakage-control policies to temperature

A novel predictive inductor multiplier for integrated circuit DC-DC converters in portable applications

A low-power, multichannel gated oscillator-based CDR for short-haul applications

Coordinated, distributed, formal energy management of chip multiprocessors

High resolution body bias techniques for reducing the impacts of leakage current and parasitic bipolar

Energy efficient strategies for deployment of a two-level wireless sensor network

Defocus-aware leakage estimation and control

Power-aware code scheduling for clusters of active disks

Inter-program optimizations for conserving disk energy

A non-uniform cache architecture for low power system design

Improving energy efficiency by making DRAM less randomly accessed

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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