NDLI: Effectiveness of low power $dual-V_{t}$ designs in nano-scale technologies under process parameter variations

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Effectiveness of low power $dual-V_{t}$ designs in nano-scale technologies under process parameter variations

Content Provider	ACM Digital Library
Author	Agarwal, Amit Kang, Kunhyuk Roy, Kaushik Bhunia, Swarup K. Gallagher, James D.
Abstract	This paper explores the effectiveness of dual-Vt design under aggressive scaling of technology, which results in significant increase in all components of leakage (subthreshold, gate and junction tunneling) while having large variations in process parameters. The present way of realizing high-Vt devices results in high junction tunneling leakage compared to low-Vt devices, which in turn may result in negligible leakage savings for dual-Vt designs in scaled technologies. Moreover, increase in process variation severely affects the yield of such designs. This paper suggests important measures that need to be incorporated in conventional dual-Vt design to achieve total leakage power improvement while ensuring yield. It also shows that different process options, such as metal gate work function engineering, are required to realize high-performance and low-leakage dual-Vt designs in sub-50nm technologies.
Starting Page	14
Ending Page	19
Page Count	6
File Format	PDF
ISBN	1595931376
DOI	10.1145/1077603.1077609
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2005-08-08
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Leakage Dual-vt Yield Process variation Metal gate
Content Type	Text
Resource Type	Article

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