NDLI: Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages

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Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages

Content Provider	ACM Digital Library
Author	Liu, Zhiyu Kursun, Volkan
Abstract	A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power consumption and enhancing evaluation speed and noise immunity in domino logic circuits. The proposed circuit technique modifies both the upper and lower boundaries of the voltage swing at the dynamic node. Meanwhile, full voltage swing signals are maintained at inputs and outputs for robust and high speed operation. Power supply, ground, and threshold voltages are simultaneously optimized to minimize the power-delay product (PDP). The proposed technique reduces the PDP by up to 51.9% as compared to the standard full-swing circuits in a 45nm CMOS technology. The active mode power consumption is reduced by up to 40.4% due to the lower switching power required to charge/discharge the dynamic node. Furthermore, the evaluation speed and noise immunity are enhanced by up to 19.4%and 39.1%, respectively, as compared to the standard fullswing circuits. The proposed low swing technique also reduces the idle mode leakage power consumption of high fan-in domino gates by up to 84.2%.
Starting Page	31
Ending Page	36
Page Count	6
File Format	PDF
ISBN	0769525237
DOI	10.1109/ISQED.2006.112
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-03-27
Access Restriction	Subscribed
Subject Keyword	Domino logic low voltage swing dual threshold voltage gate oxide leakage subthreshold leakage.
Content Type	Text
Resource Type	Article

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