NDLI: Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs

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Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs

Content Provider	ACM Digital Library
Author	Sugihara, Yuuri Kobayashi, Kazutoshi Kume, Yohei Onodera, Hidetoshi
Abstract	FPGAs in future deep submicron fabrication process will suffer from drastic speed and yield loss caused by device variations. We propose variation-aware reconfiguration which utilizes variations for performance enhancement. To utilize random variations for performance enhancement, optimizing each device from a common initial configuration is better than producing optimized configurations according to detailed measurement results because it is very hard to measure detailed variation maps chip by chip when random uncorrelated variations are dominant. In the critical path reconfiguration scheme, an initial configuration is gradually optimized chip by chip according to the delay variations. We apply the track swapping procedure to critical path reconfiguration which obtains an optimized configuration to repeat measurement and reconfiguration. First we configure all fabricated FPGAs with a common configuration data without considering variations. The configuration of each die is optimized to reroute the critical paths by choosing a faster path. To reroute a critical path we swap a wire track on a critical path with the adjacent track. It can be realized to use switch blocks with more flexibility. We implement the track swapping to VPR and experiment performance enhancement by applying the track swapping to LGSynth93 benchmark circuits. The average speed and yield enhancements are 2.57%, 26.01% respectively when the standard deviation of random variations is 10.0%.
Starting Page	257
Ending Page	257
Page Count	1
ISBN	9781595939340
DOI	10.1145/1344671.1344711
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-02-24
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Fpga Yield enhancement Routing Variation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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