NDLI: A Noise Generator for Analog-to-Digital Converter Testing

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Two Hardware Implementations for the Montgomery Modular Multiplication: Sequential versus Parallel

Analysis and Implementation of a Stochastic Multiplier for Electrical Power Measurement

A New Architecture for 2's Complement Gray Encoded Array Multiplier

Architectural Synthesis of Finite Impulse Response Digital Filters

HW/SW Codesign of Handoff Protocol for Wireless ATM Networks Based on Performance Optimization Using Genetic Algorithm

APU: Specification and Design of a Multi Algorithm ATM Policing Unit IP

Multithreaded Architectural Support for Speculative Trace Scheduling in VLIW Processors

A Novel Method for Improving the Operation Autonomy of SIMD Processing Elements

An Integrated CMOS Instrumentation Amplifier with Improved CMRR

A Continuous-Time Incremental Analog to Digital Converter

Capacitor Charge Control Technique Applied to Digitally Programmable IIR Switched-Capacitor Filter

Analog Decimator IC in Direct-form Polyphase Structure

Testability Properties of BDDs

Reducing Test Application Time through Interleaved Scan

Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy

A Software Fault Tolerance Method for Safety-Critical Systems: Effectiveness and Drawbacks

Interface Generation for Concurrent Processes During Hardware/Software Co-synthesis

A Heterogeneous and Distributed Co-Simulation Environment

A Study on Communication Issues for Systems-on-Chip

A Study on a Garbage Collector for Embedded Applications

A Noise Generator for Analog-to-Digital Converter Testing

A Statistical Sampler for Increasing Analog Circuits Observability

A Methodology for Dynamic Power Consumption Estimation Using VHDL Descriptions

Power Consumption in Point-to-Point Interconnect Architectures

Collaborative Design Using a Shared Object Spaces Infrastructure

Experiences on Analog Circuit Technology Migration and Reuse

Techniques and Mechanisms for Dynamic Reconfiguration in an Image Processor

Core Communication Interface for FPGAs

A Low-Cost FPGA Implementation of the Advanced Encryption Standard Algorithm

An IP of an Advanced Encryption Standard for Altera" Devices

Pipelined Entropy Coders for JPEG Compression

Signal Processing Applications for Embedded Java Systems

Power Management Exploration for a Block Turbo Decoder

Low-Power Control Architecture for Embedded Processors

Exception Handling with Petri Net for Digital Systems

CDFG -Petri Net Temporal Partitioning for Switching Context Applications

An Offset Self-Correction Sample and Hold Circuit for Precise Applications in Low Voltage CMOS

Operational Amplifier Power Optimization for a Given Total (Slewing plus Linear) Settling Time

A Switched-MOSFET Programmable Low-Voltage Filter

Low-Voltage ADC for Sample to Serial Interface Applications

Automatic Generation of Digital Cell Libraries

A LEGAL Algorithm Following Global Routing

Finding the Critical Delay of Combinational Blocks by Floating Vector Simulation and Path Tracing

Compression and Technology Mapping of Logic Circuits

CMOS OTA Sizing Using ACM Model in a Graphical Approach

Design of Active Inductors Using CMOS Technology

On Generating Compact, Passive Models of Frequency-Described Systems

Behavioral Modeling of Analogue and Mixed Integrated Systems with VHDL-AMS for RF Applications

On the Importance, Problems and Solutions of Pointer Synthesis

Requirements, Primitives and Models for Systems Specification

System on a Chip for Petroleum Pipeline Inspection

Combined Turbo and Convolutional Decoder Architecture for UMTS Wireless Applications

CMOS Bandgap with Base-Current Thermal Compensation

A 4 Gsamples/S with 2-4 GHz Input Bandwidth SIGE Digitizer for Radio Astronomy Applications

Minimizing the Number of Paths in BDDs

Asynchronous Circuit Design Based on the RTBT Monostable-Bistable Logic Transition Element (MOBILE)

Data Transfer and Storage Exploration for Real-Time Implementation of a Digital Audio Broadcast Receiver on a Trimedia Processor

Configurable Systems-on-Chip (CSoC)

A Structural Test Methodology for SRAM-Based FPGAs

Ultra Low-Energy Transceivers for Wireless Sensor Networks

Parametric Yield Estimation for Deep Sub- Micron VLSI Circuits

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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