NDLI: REDEFIS: a system with a redefinable instruction set processor

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Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration

REDEFIS: a system with a redefinable instruction set processor

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REDEFIS: a system with a redefinable instruction set processor

Content Provider	ACM Digital Library
Author	MURAKAMI, Kazuaki MATSUO, Takuma HASHINAGA, Toshihiko KANDO, Takayuki GAUTHIER, Lovic GOULART FERREIRA, Victor M.
Abstract	The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight performance or power constraints, or too complex to design in short TAT/TTM. REDEFIS is a HW/SW design platform for high level, efficient implementation of ASIPs/engines for SoC systems. It is composed of a reconfigurable instruction-set processor, capable to redefine its ISA according to the user application written in high level C language, and a set of design tools (an ISA Generator and a retargetable compiler). These processors can be used as flexible engines in embedded MPSoC systems, where its ISA is fully customized and design is done at high level C (no HDL writing is necessary). In this paper we present the Redefis design platform and an implementation of our dynamically reconfigurable ISA processor (codename Vulcan). Our results demonstrate the effectiveness of the system for encryption and bitwise applications.
Starting Page	14
Ending Page	19
Page Count	6
File Format	PDF
ISBN	1595934790
DOI	10.1145/1150343.1150354
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-08-28
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Isa customization High performance Soc Low power Dynamically reconfigurable processor
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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