NDLI: Robust low power computing in the nanoscale era

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Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration

REDEFIS: a system with a redefinable instruction set processor

Dynamic task binding for hardware/software reconfigurable networks

Ant colony based routing architecture for minimizing hot spots in NOCs

An ultra low-power class-AB sinh integrator

Bias circuit design for low-voltage cascode transistors

Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture

MDA-based approach for embedded software generation from a UML/MOF repository

Exploiting general coefficient representation for the optimal sharing of partial products in MCMs

Single event transients in dynamic logic

Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing

The re-definition of low power design for HPC: a paradigm shift

Formal verification for real-world designs

Asynchronous circuit design on reconfigurable devices

Infrastructure for dynamic reconfigurable systems: choices and trade-offs

Application driven traffic modeling for NoCs

Ultra low-voltage ultra low-power CMOS threshold voltage reference

A differential switched-capacitor amplifier with programmable gain and output offset voltage

Aspect-oriented design in systemC: implementation and applications

Hardware support in a middleware for distributed and real-time embedded applications

A cell library for low power high performance CMOS voltage-mode quaternary logic

A cryptography core tolerant to DFA fault attacks

Effects of digital switching noise on analog voltage references in mixed-signal CMOS ICs

High performance silicon MEMS for niche market applications

Robust low power computing in the nanoscale era

FPGA architecture for static background subtraction in real time

Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration

Area and performance optimization of a generic network-on-chip architecture

A test chip for automatic MOSFET mismatch characterization

4GHz continuous-time bandpass delta-sigma modulator for directly high IF A/D conversion

SAEPTUM: verification of ELAN hardware specifications using the proof assistant PVS

Cache performance impacts for stack machines in embedded systems

On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives

Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates

A band-pass Gm-C Filter design based on gm/ID methodology and characterization

Run-time reconfigurabilility and other future trends

Implementation of dispatching algorithms for elevator systems using reconfigurable architectures

Power constrained design optimization of analog circuits based on physical gm/ID characteristics

A general domain CMOS companding integrator

A fast SAT solver algorithm best suited to reconfigurable hardware

ByZFAD: a low switching activity architecture for shift-and-add multipliers

Evaluation of SEU and crosstalk effects in network-on-chip switches

Low maintenance verification

Fast disjoint transistor networks from BDDs

Using a software testing technique to identify registers for partial scan implementation

Razor: a low-power pipeline based on circuit-level timing speculation

Using NEXUS compliant debuggers for real time fault injection on microprocessors

Robust low power computing in the nanoscale era

Content Provider	ACM Digital Library
Author	Austin, Todd
Abstract	This tutorial will present recent results in robust low power computing. The perspective will be microarchitectural: what limitations does it put on the microarchitecture and what can the microarchitect do to reduce the dependency on power and improve robustness? The tutorial will start with a technology overview that charts future trends in power and reliability. We will present a summary of prior research in dynamic power reduction in microarchitectures, and give some examples of industrial solutions. We will also review prior research in microarchitectural reduction of leakage performed by us and others. While the continued scaling that Moore's Law predicts is in many ways good for reducing power, scaling also reduces reliability by increasing uncertainty in device performance. Therefore, in order to take advantage of scaling, it will be necessary to compute in the presence of various types of silicon-related faults. Two that are particularly important are single-event upsets, and, even more serious, gates that will not meet their specifications. We will review techniques to provide robustness in light of these trends. In particular, we will revisit techniques developed by the fault-tolerant community as well as newer ideas in timing speculation, exemplified by our Razor research.The tutorial is intended for computer architects and circuit designers interested in a better understanding of current reliability challenges and emerging technologies to address them.
Starting Page	6
Ending Page	6
Page Count	1
File Format	PDF
ISBN	1595934790
DOI	10.1145/1150343.1150352
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-08-28
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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