NDLI: Test function specification in synthesis

Please wait, while we are loading the content...

The VHDL validation suite

NES: the behavioral model for the formal semantics of a hardware design language UDL/I

An intermediate representation for behavioral synthesis

Optimization by simulated evolution with applications to standard cell placement

Stochastic evolution: a fast effective heuristic for some generic layout problems

Integrated placement for mixed macro cell and standard cell designs

A new simultaneous circuit partitioning and chip placement approach based on simulated annealing

Efficient implementation of a BDD package

Sequential circuit verification using symbolic model checking

Shared binary decision diagram with attributed edges for efficient Boolean function manipulation

Relative scheduling under timing constraints

Optimum and heuristic data path scheduling under resource constraints

The combination of scheduling, allocation, and mapping in a single algorithm

A linear program driven scheduling and allocation method followed by an interconnect optimization algorithm

Timing driven placement using complete path delays

An adaptive timing-driven layout for high speed VLSI

A new min-cut placement algorithm for timing assurance layout design meeting net length constraint

Performance-driven constructive placement

MHERTZ: a new optimization algorithm for floorplanning and global routing

Analysis and design of latch-controlled synchronous digital circuits

Timing verification using HDTV

Timing analysis in precharge/unate networks

Coded time-symbolic simulation using shared binary decision diagram

Design management based on design traces

Meta data management in the NELSIS CAD framework

An intelligent component database for behavioral synthesis

Design data management in a CAD framework environment

Memory, control and communications synthesis for scheduled algorithms

A generalized interconnect model for data path synthesis

Automatic operator configuration in the synthesis of pipelined architectures

An optimal algorithm for floorplan area optimization

An analytical approach to floorplan design and optimization

Pad placement and ring routing for custom chip layout

Comparing structurally different views of a VLSI design

Verification of interacting sequential circuits

Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuits

Is redundancy necessary to reduce delay

Test function specification in synthesis

Layout synthesis of MOS digital cells

A practical online design rule checking system

Design and performance evaluation of new massively parallel VLSI mask verification algorithms in JIGSAW

Circuit extraction on a message-based multiprocessor

SKILL: A CAD system extension language

BREL—a Prolog knowledge-based system shell for VLSI CAD

Design methodology management—a CAD framework initiative perspective

Boolean resubstitution with permissible functions and binary decision diagrams

Reduced offsets for two-level multi-valued logic minimization

The use of observability and external don't cares for the simplification of multi-level networks

An entropy measure for the complexity of multi-output Boolean functions

A data path layout assembler for high performance DSP circuits

Global routing considerations in a cell synthesis system

Benchmarks for cell synthesis

New algorithm for overlapping cell treatment in hierarchical CAD data/electron beam exposure data conversion

Design of repairable and fully diagnosable folded PLAs for yield enhancement

NASFLOW, a simulation tool for silicon technology development

Timing optimization for multi-level combinational networks

Logic optimization algorithm by linear programming approach

Delay and area optimization in standard-cell design

Algorithms for library-specific sizing of combinational logic

A heuristic algorithm for the fanout problem

A depth-decreasing heuristic for combinational logic: or how to convert a ripple-carry adder into a carry-lookahead adder or anything in-between

Multilevel synthesis minimizing the routing factor

Layout compaction with attractive and repulsive constraints

A hierarchy preserving hierarchical compactor

An $O(n^{1.5}logn)$ 1-d compaction algorithm

Datapath generator based on gate-level symbolic layout

Parallel circuit simulation using hierarchical relaxation

PARASPICE: a parallel circuit simulator for shared-memory multiprocessors

Waveform moment methods for improved interconnection analysis

System simulation of printed circuit boards including packages and connectors

A framework for industrial layout generators

Organized C: A unified method of handling data in CAD algorithms and databases

An object-oriented VHDL design environment

An object-oriented kernel for an integrated design and process planning system

Percolation based synthesis

Synthesis using path-based scheduling: algorithms and exercises

Global hardware synthesis from behavioral dataflow descriptions

A transistor reordering technique for gate matrix layout

PALACE: a layout generator for SCVS logic blocks

LiB: a cell layout generator

Techniques for unit-delay compiled simulation

Distributed and parallel demand driven logic simulation

LECSIM: a levelized event driven compiled logic simulation

Data path allocation based on bipartite weighted matching

A global, dynamic register allocation and binding for a data path synthesis system

Data path tradeoffs using MABAL

Symbolic simulation—techniques and applications

An efficient delay test generation system for combinational logic circuits

Automatic incorporation of on-chip testability circuits

Proofs: a fast, memory efficient sequential circuit fault simulator

Architecture synthesis of high-performance application-specific processors

High-level synthesis: technology transfer to industry

ASSURE: automated design for dependability

Constraint generation for routing analog circuits

Segmented channel routing

Clock routing for high-performance ICs

Sequential test generation at the register-transfer and logic levels

Behavioral fault simulation in VHDL

Speed up of test generation using high-level primitives

A unified approach to the decomposition and re-decomposition of sequential machines

Corolla based circuit partitioning and resynthesis

Chortle: a technology mapping program for lookup table-based field programmable gate arrays

Logic synthesis for programmable gate arrays

A gridless router for industrial design rules

Layout optimization by pattern modification

A channel/switchbox definition algorithm for building-block layout

New placement and global routing algorithms for standard cell layouts

A hardware implementation of gridless routing based on content addressable memory

PHIGURE: a parallel hierarchical global router

Automatic test generation using quadratic 0-1 programming

SOPRANO: an efficient automatic test pattern generator for stuck-open faults in CMOS combinational circuits

EST: The new frontier in automatic test-pattern generation

The influences of fault type and topology on fault model performance and the implications to test and testable design

Abstract data types and high-level synthesis

Failure recovery in the MICON system

The FSM network model for behavioral synthesis of control-dominated machines

MISER: an integrated three layer gridless channel router and compactor

A multi-layer router utilizing over-cell areas

General models and algorithms for over-the-cell routing in standard cell design

A parallel pattern mixed-level fault simulator

Extension of the critical path tracing algorithm

BIST PLAs, pass or fail—a case study

A variable observation time method for testing delay faults

A fault analysis method for synchronous sequential circuits

On synthesizing and identifying stuck-open testable CMOS combinational circuits (extended abstract)

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in