NDLI: Is redundancy necessary to reduce delay

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A parallel pattern mixed-level fault simulator

Extension of the critical path tracing algorithm

BIST PLAs, pass or fail—a case study

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A fault analysis method for synchronous sequential circuits

On synthesizing and identifying stuck-open testable CMOS combinational circuits (extended abstract)

Is redundancy necessary to reduce delay

Content Provider	ACM Digital Library
Author	Saldanha, Alexander Malik, Sharad Keutzer, Kurt
Abstract	Logic optimization procedures principally attempt to optimize three criteria: performance, area and testability. The relationship between area optimization and testability has recently been explored. As to the relationship between performance and testability, experience has shown that performance optimizations can, and do in practice, introduce single stuck-at-fault redundancies into designs. Are these redundancies necessary to increase performance or are they only an unnecessary byproduct of performance optimization? In this paper we give a constructive resolution of this question in the form of an algorithm that takes as input a combinational circuit and returns an irredundant circuit that is as fast. We demonstrate the utility of this algorithm on a well known circuit, the carry-skip adder, and present a novel irredundant design of that adder. As our algorithm may either increase or decrease circuit area, we leave unresolved the question as to whether every circuit has an irredundant circuit that is at least as fast and is of equal or lesser area.
Starting Page	228
Ending Page	234
Page Count	7
File Format	PDF
ISBN	0897913639
DOI	10.1145/123186.128295
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1991-01-03
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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