NDLI: StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems

Please wait, while we are loading the content...

Highly energy and performance efficient embedded computing through approximately correct arithmetic: a mathematical foundation and preliminary experimental validation

Active control and digital rights management of integrated circuit IP cores

ZebraNet and beyond: applications and systems support for mobile, dynamic networks

A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization

Exploring and predicting the architecture/optimising compiler co-design space

Compiling custom instructions onto expression-grained reconfigurable architectures

Decoupled root scanning in multi-processor systems

Efficient code caching to improve performance and energy consumption for java applications

Control flow optimization in loops using interval analysis

Multiple sleep mode leakage control for cache peripheral circuits in embedded processors

A low-power parallel design of discrete wavelet transform using subthreshold voltage technology

Power on demand for mobile computing devices

VESPA: portable, scalable, and flexible FPGA-based vector processors

SoC-C: efficient programming abstractions for heterogeneous multicore systems on chip

Cache-aware cross-profiling for java processors

Efficient vectorization of SIMD programs with non-aligned and irregular data access hardware

Design space exploration for field programmable compressor trees

Power management of MEMS-based storage devices for mobile systems

Dynamic coprocessor management for FPGA-enhanced compute platforms

Predictable programming on a precision timed architecture

Comprehensive isomorphic subtree enumeration

Multi-granularity sampling for simulating concurrent heterogeneous applications

Execution context optimization for disk energy

StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems

Content Provider	ACM Digital Library
Author	Blome, Jason Feng, Shuguang Gupta, Shantanu Mahlke, Scott Ansari, Amin
Abstract	Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip temperatures. Given that most wearout mechanisms that plague semiconductor devices are highly dependent on these parameters, significantly higher failure rates are projected for future technology generations. Traditional techniques for dealing with device failures have relied on coarse-grained redundancy to maintain service in the face of failed components. In this work, we challenge this practice by identifying its inability to scale to high failure rate scenarios and investigate the advantages of finer-grained configurations. We use this study to motivate the design of StageNet, an embedded CMP architecture designed from its inception with reliability as a first class design constraint. StageNet relies on a reconfigurable network of replicated processor pipeline stages to maximize the useful lifetime of the chip, gracefully degrading performance toward end of life. This paper addresses the microarchitecture of the basic building block of StageNet, named StageNetSlice, which is a processor core comprised of networked pipeline stages. A naive slice design results in approximately 4X slowdown verses a traditional processor due to longer communication delays in the pipeline. However, several small design changes that eliminate inter-stage communication paths and minimize communication bandwidth reduce this overhead to 11% on average while providing high levels of fine-grain adaptability.
Starting Page	1
Ending Page	10
Page Count	10
File Format	PDF
ISBN	9781605584690
DOI	10.1145/1450095.1450099
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-10-19
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Multicore Architecture Reliability Pipeline
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Stagenetslice: A reconfigurable microarchitecture building block for resilient cmp systems (2008)

Stagenetslice: A reconfigurable microarchitecture building block for resilient cmp systems (2008)

Resilient Chip Multiprocessors with Mixed-Grained Reconfigurability

StageWeb: Interweaving pipeline stages into a wearout and variation tolerant CMP fabric

Erasing Core Boundaries for Robust and Configurable Performance

UnSync-CMP: Multicore CMP Architecture for Energy-Efficient Soft-Error Reliability

A reconfigurable architecture for multicore systems

High-Assurance Reconfigurable Multicore Processor Based Systems

The stagenet fabric for constructing resilient multicore systems," micro (2008).

StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems

Similar Documents

Stagenetslice: A reconfigurable microarchitecture building block for resilient cmp systems (2008)

Stagenetslice: A reconfigurable microarchitecture building block for resilient cmp systems (2008)

Resilient Chip Multiprocessors with Mixed-Grained Reconfigurability

StageWeb: Interweaving pipeline stages into a wearout and variation tolerant CMP fabric

Erasing Core Boundaries for Robust and Configurable Performance

UnSync-CMP: Multicore CMP Architecture for Energy-Efficient Soft-Error Reliability

A reconfigurable architecture for multicore systems

High-Assurance Reconfigurable Multicore Processor Based Systems

The stagenet fabric for constructing resilient multicore systems," micro (2008).

StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems