NDLI: Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms

Please wait, while we are loading the content...

Delay Scalings and Mean-Field Limits in Networked Systems

A Low-Complexity Approach to Distributed Cooperative Caching with Geographic Constraints

Hieroglyph: Locally-Sufficient Graph Processing via Compute-Sync-Merge

Investigation of the 2016 Linux TCP Stack Vulnerability at Scale

Fluid-Model-Based Car Routing for Modern Ridesharing Systems

Online Optimization for Markets and the Cloud: Theory and Practice

Stein's Method for Mean-Field Approximations in Light and Heavy Traffic Regimes

Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms

Hadoop on Named Data Networking: Experience and Results

On Gradient-Based Optimization: Accelerated, Distributed, Asynchronous and Stochastic

Portfolio-driven Resource Management for Transient Cloud Servers

Matrix Factorization at the Frontier of Non-convex Optimizations: Abstract for SIGMETRICS 2017 Rising Star Award Talk

Outward Influence and Cascade Size Estimation in Billion-scale Networks

A Case Study in Power Substation Network Dynamics

Routing Money, Not Packets: A Tutorial on Internet Economics

Optimal Service Elasticity in Large-Scale Distributed Systems

A Simple Yet Effective Balanced Edge Partition Model for Parallel Computing

Characterizing and Modeling Patching Practices of Industrial Control Systems

Pseudo-Separation for Assessment of Structural Vulnerability of a Network

Expected Values Estimated via Mean-Field Approximation are 1/N-Accurate: Extended Abstract

Exploiting Data Longevity for Enhancing the Lifetime of Flash-based Storage Class Memory

Using Burstable Instances in the Public Cloud: Why, When and How?

Optimal Posted Prices for Online Cloud Resource Allocation

Accelerating Performance Inference over Closed Systems by Asymptotic Methods

Persistent Spread Measurement for Big Network Data Based on Register Intersection

Queue-Proportional Sampling: A Better Approach to Crossbar Scheduling for Input-Queued Switches

Overcommitment in Cloud Services Bin packing with Chance Constraints

Security Game with Non-additive Utilities and Multiple Attacker Resources

On the Capacity Requirement for Arbitrary End-to-End Deadline and Reliability Guarantees in Multi-hop Networks

Analysis of a Stochastic Model of Replication in Large Distributed Storage Systems: A Mean-Field Approach

Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms

Dandelion: Redesigning the Bitcoin Network for Anonymity

On Optimal Two-Sided Pricing of Congested Networks

Quality and Cost of Deterministic Network Calculus: Design and Evaluation of an Accurate and Fast Analysis

Deconstructing the Energy Consumption of the Mobile Page Load

Optimizing Speculative Execution of Deadline-Sensitive Jobs in Cloud

A Spot Capacity Market to Increase Power Infrastructure Utilization in Multi-Tenant Data Centers

Hour-Ahead Offering Strategies in Electricity Market for Power Producers with Storage and Intermittent Supply

Why "Some" Like It Hot Too: Thermal Attack on Data Centers

Incentivizing Reliable Demand Response with Customers' Uncertainties and Capacity Planning

A Study on Performance and Power Efficiency of Dense Non-Volatile Caches in Multi-Core Systems

Scheduling Coflows in Datacenter Networks: Improved Bound for Total Weighted Completion Time

Characterizing 3D Floating Gate NAND Flash

ECF: An MPTCP Path Scheduler to Manage Heterogeneous Paths

Simplex Queues for Hot-Data Download

An Empirical Analysis of Facebook's Free Basics

Multipath TCP on a VANET: A Performance Study

A Fast, Small, and Dynamic Forwarding Information Base

HFTraC: High-Frequency Traffic Control

Adaptive TTL-Based Caching for Content Delivery

Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms

Content Provider	ACM Digital Library
Author	Subramanian, Lavanya Khan, Samira Ghose, Saugata Pekhimenko, Gennady Mutlu, Onur Lee, Donghyuk Ausavarungnirun, Rachata Seshadri, Vivek
Abstract	Variation has been shown to exist across the cells within a modern DRAM chip. Prior work has studied and exploited several forms of variation, such as manufacturing-process- or temperature-induced variation. We empirically demonstrate a new form of variation that exists within a real DRAM chip, induced by the design and placement of different components in the DRAM chip: different regions in DRAM, based on their relative distances from the peripheral structures, require different minimum access latencies for reliable operation. In particular, we show that in most real DRAM chips, cells closer to the peripheral structures can be accessed much faster than cells that are farther. We call this phenomenon design-induced variation in DRAM. Our goals are to i) understand design-induced variation that exists in real, state-of-the-art DRAM chips, ii) exploit it to develop low-cost mechanisms that can dynamically find and use the lowest latency at which to operate a DRAM chip reliably, and, thus, iii) improve overall system performance while ensuring reliable system operation. To this end, we first experimentally demonstrate and analyze designed-induced variation in modern DRAM devices by testing and characterizing 96 DIMMs (768 DRAM chips). Our experimental study shows that i) modern DRAM chips exhibit design-induced latency variation in both row and column directions, ii) access latency gradually increases in the row direction within a DRAM cell array (mat) and this pattern repeats in every mat, and iii) some columns require higher latency than others due to the internal hierarchical organization of the DRAM chip. Our characterization identifies DRAM regions that are vulnerable to errors, if operated at lower latency, and finds consistency in their locations across a given DRAM chip generation, due to design-induced variation. Variations in the vertical and horizontal dimensions, together, divide the cell array into heterogeneous-latency regions, where cells in some regions require longer access latencies for reliable operation. Reducing the latency uniformly across all regions in DRAM would improve performance, but can introduce failures in the inherently slower regions that require longer access latencies for correct operation. We refer to these inherently slower regions of DRAM as design-induced vulnerable regions. Based on our extensive experimental analysis, we develop two mechanisms that reliably reduce DRAM latency. First, DIVI Profiling uses runtime profiling to dynamically identify the lowest DRAM latency that does not introduce failures. DIVA Profiling exploits design-induced variation and periodically profiles only the vulnerable regions to determine the lowest DRAM latency at low cost. It is the first mechanism to dynamically determine the lowest latency that can be used to operate DRAM reliably. DIVA Profiling reduces the latency of read/write requests by 35.1%/57.8%, respectively, at 55C. Our second mechanism, DIVA Shuffling, shuffles data such that values stored in vulnerable regions are mapped to multiple error-correcting code (ECC) codewords. As a result, DIVA Shuffling can correct 26% more multi-bit errors than conventional ECC. Combined together, our two mechanisms reduce read/write latency by 40.0%/60.5%, which translates to an overall system performance improvement of 14.7%/13.7%/13.8% (in 2-/4-/8-core systems) over a variety of workloads, while ensuring reliable operation.
Starting Page	54
Ending Page	54
Page Count	1
File Format	PDF
ISBN	9781450350327
DOI	10.1145/3078505.3078533
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2017-06-05
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Fault tolerance Latency variation Dram Memory systems
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in