NDLI: From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware

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Reviewers

Achieving Out-of-Order Performance with Almost In-Order Complexity

Fetch-Criticality Reduction through Control Independence

A Two-Level Load/Store Queue Based on Execution Locality

Self-Optimizing Memory Controllers: A Reinforcement Learning Approach

A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems

Technology-Driven, Highly-Scalable Dragonfly Topology

Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks

Polymorphic On-Chip Networks

Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory

TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory

Flexible Decoupled Transactional Memory Support

Corona: System Implications of Emerging Nanophotonic Technology

Microcoded Architectures for Ion-Tap Quantum Computers

Running a Quantum Circuit at the Speed of Data

ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency

Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

Counting Dependence Predictors

Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support

iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures

MIRA: A Multi-layered On-Chip Interconnect Router Architecture

Rerun: Exploiting Episodes for Lightweight Memory Race Recording

Atom-Aid: Detecting and Surviving Atomicity Violations

DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Ef?ciently

Intra-disk Parallelism: An Idea Whose Time Has Come

Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments

Improving NAND Flash Based Disk Caches

Online Estimation of Architectural Vulnerability Factor for Soft Errors

A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime

Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors

Flexible Hardware Acceleration for Instruction-Grain Program Monitoring

VEAL: Virtualized Execution Accelerator for Loops

From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware

Software-Controlled Priority Characterization of POWER5 Processor

Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction

Atomic Vector Operations on Chip Multiprocessors

3D-Stacked Memory Architectures for Multi-core Processors

Author Index

Publisher's Information

From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware

Content Provider	ACM Digital Library
Author	Yuan, Liwei Chen, Haibo Chong, Frederic T. Zang, Binyu Yew, Pen-chung Wu, Xi
Abstract	Dynamic information flow tracking (also known as taint tracking) is an appealing approach to combat various security attacks. However, the performance of applications can severely degrade without hardware support for tracking taints. This paper observes that information flow tracking can be efficiently emulated using deferred exception tracking in microprocessors supporting speculative execution. Based on this observation, we propose SHIFT, a low-overhead, software-based dynamic information flow tracking system to detect a wide range of attacks. The key idea is to treat tainted state (describing untrusted data) as speculative state (describing deferred exceptions). SHIFT leverages existing architectural support for speculative execution to track tainted state in registers and needs to instrument only load and store instructions to track tainted state in memory using a bitmap, which results in significant performance advantages. Moreover, by decoupling mechanisms for taint tracking from security policies, SHIFT can detect a wide range of exploits, including high-level semantic attacks. We have implemented SHIFT using the Itanium processor, which has support for deferred exceptions, and by modifying GCC to instrument loads and stores. A security assessment shows that SHIFT can detect both low-level memory corruption exploits as well as high-level semantic attacks with no false positives. Performance measurements show that SHIFT incurs about 1% overhead for server applications. The performance slowdown for SPEC-INT2000 is 2.81X and 2.27X for tracking at byte-level and wordlevel respectively. Minor architectural improvements to the Itanium processor (adding three simple instructions) can reduce the performance slowdown down to 2.32X and 1.8X for byte-level and word-level tracking, respectively.
Starting Page	401
Ending Page	412
Page Count	12
File Format	PDF
ISBN	9780769531748
ISSN	10636897
DOI	10.1109/ISCA.2008.18
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-06-21
Access Restriction	Subscribed
Subject Keyword	Dynamic information flow tracking taint tracking speculative execution deferred exception
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware

From Speculation to Security:Practical and Efficient Information Flow Tracking Using Speculative Hardware

From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware (2008)

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From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware

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