NDLI: Fetch-Criticality Reduction through Control Independence

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Achieving Out-of-Order Performance with Almost In-Order Complexity

Fetch-Criticality Reduction through Control Independence

A Two-Level Load/Store Queue Based on Execution Locality

Self-Optimizing Memory Controllers: A Reinforcement Learning Approach

A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems

Technology-Driven, Highly-Scalable Dragonfly Topology

Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks

Polymorphic On-Chip Networks

Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory

TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory

Flexible Decoupled Transactional Memory Support

Corona: System Implications of Emerging Nanophotonic Technology

Microcoded Architectures for Ion-Tap Quantum Computers

Running a Quantum Circuit at the Speed of Data

ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency

Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

Counting Dependence Predictors

Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support

iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures

MIRA: A Multi-layered On-Chip Interconnect Router Architecture

Rerun: Exploiting Episodes for Lightweight Memory Race Recording

Atom-Aid: Detecting and Surviving Atomicity Violations

DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Ef?ciently

Intra-disk Parallelism: An Idea Whose Time Has Come

Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments

Improving NAND Flash Based Disk Caches

Online Estimation of Architectural Vulnerability Factor for Soft Errors

A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime

Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors

Flexible Hardware Acceleration for Instruction-Grain Program Monitoring

VEAL: Virtualized Execution Accelerator for Loops

From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware

Software-Controlled Priority Characterization of POWER5 Processor

Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction

Atomic Vector Operations on Chip Multiprocessors

3D-Stacked Memory Architectures for Multi-core Processors

Author Index

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Fetch-Criticality Reduction through Control Independence

Content Provider	ACM Digital Library
Author	Navale, Nitin Agarwal, Mayank Frank, Matthew I. Malik, Kshitiz
Abstract	Architectures that exploit control independence (CI) promise to remove in-order fetch bottlenecks, like branch mispredicts, instruction-cache misses and fetch unit stalls, from the critical path of single-threaded execution. By exposing more fetch options, however, CI architectures also expose more performance tradeoffs. These tradeoffs make it hard to design policies that deliver good performance.This paper presents a criticality-based model for reasoning about CI architectures, and uses that model to describe the tradeoffs between gains from control independence versus increased costs of honoring data dependences. The model is then used to derive the design of a criticality-aware task selection policy that strikes the right balance between fetch-criticality and execute-criticality. Finally, the papervalidates the model by attacking branch-misprediction induced fetch-criticality through the above derived spawnpolicy. This leads to as high as 100% improvements in performance, and in the region of 40% or more improvements for four of the benchmarks where this is the main problem. Criticality analysis shows that this improvement arises due to reduced fetch-criticality.
Starting Page	13
Ending Page	24
Page Count	12
File Format	PDF
ISBN	9780769531748
ISSN	10636897
DOI	10.1109/ISCA.2008.39
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-06-21
Access Restriction	Subscribed
Subject Keyword	Control independence fetch-criticality implicit parallelization
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Fetch-Criticality Reduction through Control Independence

Fetch-Criticality Reduction through Control Independence

C ○ 2009 mayank agarwalidentifying, quantifying, extracting and enhancing implicit parallelism by.

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Speculative parallelization of partial reduction variables

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Fetch-Criticality Reduction through Control Independence

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